JPS5566134A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS5566134A
JPS5566134A JP13932878A JP13932878A JPS5566134A JP S5566134 A JPS5566134 A JP S5566134A JP 13932878 A JP13932878 A JP 13932878A JP 13932878 A JP13932878 A JP 13932878A JP S5566134 A JPS5566134 A JP S5566134A
Authority
JP
Japan
Prior art keywords
gate
insulated gate
compensation circuit
conduction type
plus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13932878A
Other languages
Japanese (ja)
Inventor
Kenji Kawatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13932878A priority Critical patent/JPS5566134A/en
Publication of JPS5566134A publication Critical patent/JPS5566134A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Abstract

PURPOSE:To realize the low power consumption as well as the low clock frequency by drawing out the bias output from the joint of the compensation circuit consisting of the complementary insulated gate FET in which the drain and the gate plus the source and the gate are connected between two active voltage supply terminals. CONSTITUTION:Uni-conduction type insulated gate FETQ5 using clock pluse phi as the gate input plus logic block 6 formed with opposite conduction type insulated gate FETQ6 are connected in series between active voltage supply terminals VDD and VSS, and output terminal 8 is led out from connection part 7. Then uni-conduction type insulated gate FETQ7 is connected between terminals VDD and 8, and the bias compensation circuit is connected to the gate. The compensation circuit consists of complementary insulated gate FETQ8 and Q9 in which the drain and the gate plus the source and the gate are connected between terminals VDD and VSS, and the bias output is drawn out from joint 10. As a result, the power consumption can be decreased along with lowering of the clock frequency.
JP13932878A 1978-11-14 1978-11-14 Logic circuit Pending JPS5566134A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13932878A JPS5566134A (en) 1978-11-14 1978-11-14 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13932878A JPS5566134A (en) 1978-11-14 1978-11-14 Logic circuit

Publications (1)

Publication Number Publication Date
JPS5566134A true JPS5566134A (en) 1980-05-19

Family

ID=15242747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13932878A Pending JPS5566134A (en) 1978-11-14 1978-11-14 Logic circuit

Country Status (1)

Country Link
JP (1) JPS5566134A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01120124A (en) * 1987-10-07 1989-05-12 Northern Telecom Ltd Current mirror bias charge logic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01120124A (en) * 1987-10-07 1989-05-12 Northern Telecom Ltd Current mirror bias charge logic circuit

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