JPS5563438A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5563438A
JPS5563438A JP13702778A JP13702778A JPS5563438A JP S5563438 A JPS5563438 A JP S5563438A JP 13702778 A JP13702778 A JP 13702778A JP 13702778 A JP13702778 A JP 13702778A JP S5563438 A JPS5563438 A JP S5563438A
Authority
JP
Japan
Prior art keywords
fed
output
signal
information
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13702778A
Other languages
Japanese (ja)
Inventor
Fumitaka Sato
Tadayuki Soejima
Koichi Higo
Hidemi Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13702778A priority Critical patent/JPS5563438A/en
Publication of JPS5563438A publication Critical patent/JPS5563438A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure the constitution simply and with low cost, by avoiding the necessity to shunt the information stored in the fixed address area in advance and keeping the information of intermediate result for data processing in the main memory unit, in executing the office instruction.
CONSTITUTION: The data read out from the main memory unit MM is once stored in MDR 10 via the selector 110 and the output of MDR is fed to the bus. Further, the address information is stored in MAR 103 under the control of microprogram and the output is fed to MM as MM designation address. After the mask processing with PSW in PSWR 104 with input to the external interruption signal processing circuit 108, the said output is fed to the signal test circuit 109. The signal test circuit 109 collects the branch condition of microprogram among the signal of CPU each section and selects a given signal according to the designation of microinstruction to feed it to the sequence circuit.
COPYRIGHT: (C)1980,JPO&Japio
JP13702778A 1978-11-07 1978-11-07 Information processor Pending JPS5563438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13702778A JPS5563438A (en) 1978-11-07 1978-11-07 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13702778A JPS5563438A (en) 1978-11-07 1978-11-07 Information processor

Publications (1)

Publication Number Publication Date
JPS5563438A true JPS5563438A (en) 1980-05-13

Family

ID=15189123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13702778A Pending JPS5563438A (en) 1978-11-07 1978-11-07 Information processor

Country Status (1)

Country Link
JP (1) JPS5563438A (en)

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