JPS5559745A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5559745A
JPS5559745A JP13361378A JP13361378A JPS5559745A JP S5559745 A JPS5559745 A JP S5559745A JP 13361378 A JP13361378 A JP 13361378A JP 13361378 A JP13361378 A JP 13361378A JP S5559745 A JPS5559745 A JP S5559745A
Authority
JP
Japan
Prior art keywords
wall
substrate
chip
resin
cap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13361378A
Other languages
Japanese (ja)
Other versions
JPS5837694B2 (en
Inventor
Junichi Kasai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53133613A priority Critical patent/JPS5837694B2/en
Publication of JPS5559745A publication Critical patent/JPS5559745A/en
Publication of JPS5837694B2 publication Critical patent/JPS5837694B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: To improve reliability, by simplifying sealing work and by bettering airtight properties by installing a wall for surrounding a semiconductor chip mounted to a mounting substrate and a wall for enclosing the substrate to a cap for housing the semiconductor chip and by filling resin between both walls.
CONSTITUTION: A semiconductor chip 3 is fixed to a mounting substrate 2 in ceramics, etc. provided with connecting-pins 1 and wiring. A cap 7 is prepared which is equipped with the first wall 8 surrounding the chip 3 and the second wall 9 enclosing the substrate in a shape that is higher than the wall 8 only by the thickness of the substrate and is integrally formed with cemarics or metal, and half- hardening or liquefied resin 10 is filled to a void between the first and second walls. The substrate to which the chip 3 is fixed is turned upside down and inserted into the cap, and the resin is hardened by heat treatment. The resin does not flow into space that there is no chip because air around the chip surrounded by means of the first wall 8 expands and is pushed out from a clearance between the wall and the substrate when heat treatment.
COPYRIGHT: (C)1980,JPO&Japio
JP53133613A 1978-10-30 1978-10-30 semiconductor equipment Expired JPS5837694B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53133613A JPS5837694B2 (en) 1978-10-30 1978-10-30 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53133613A JPS5837694B2 (en) 1978-10-30 1978-10-30 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS5559745A true JPS5559745A (en) 1980-05-06
JPS5837694B2 JPS5837694B2 (en) 1983-08-18

Family

ID=15108896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53133613A Expired JPS5837694B2 (en) 1978-10-30 1978-10-30 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5837694B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58120659U (en) * 1982-02-12 1983-08-17 株式会社日立製作所 Hybrid integrated circuit package
JPS6332952A (en) * 1986-07-25 1988-02-12 Nec Corp Package for hybrid ic
US5585669A (en) * 1991-06-17 1996-12-17 U.S. Philips Corporation Semiconductor chip card having selective encapsulation

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6111772U (en) * 1984-06-25 1986-01-23 株式会社日立国際電気 Resistance heating element support structure in single crystal pulling growth equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54113372U (en) * 1978-01-26 1979-08-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54113372U (en) * 1978-01-26 1979-08-09

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58120659U (en) * 1982-02-12 1983-08-17 株式会社日立製作所 Hybrid integrated circuit package
JPS6332952A (en) * 1986-07-25 1988-02-12 Nec Corp Package for hybrid ic
US5585669A (en) * 1991-06-17 1996-12-17 U.S. Philips Corporation Semiconductor chip card having selective encapsulation

Also Published As

Publication number Publication date
JPS5837694B2 (en) 1983-08-18

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