JPS5552582A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5552582A
JPS5552582A JP12432278A JP12432278A JPS5552582A JP S5552582 A JPS5552582 A JP S5552582A JP 12432278 A JP12432278 A JP 12432278A JP 12432278 A JP12432278 A JP 12432278A JP S5552582 A JPS5552582 A JP S5552582A
Authority
JP
Japan
Prior art keywords
block
memory
access
address
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12432278A
Other languages
Japanese (ja)
Inventor
Takeshi Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12432278A priority Critical patent/JPS5552582A/en
Publication of JPS5552582A publication Critical patent/JPS5552582A/en
Pending legal-status Critical Current

Links

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To make it possible to remove coordinating restraint between address registers and block units by controlling access to block units through pointers of an address supply part.
CONSTITUTION: For example, when address register 3-2 attains access to block register 2-0, the block memory of main memory 1 is transferred to block memory 2-1 of a buffer memory and the output of pointer 5-0 is inverted to a high level; and access to block memory 2-1 is attained by address register 3-1 and the output of pointer 5-1 is inverted. According to those high-level outputs, replacement circuit 7 selects block register 2-i when registers 3-2 and 3-1 are in a cross mode exceeding a block limit or other address registers are attaining access, and also inverts outputs of pointers 5-0 and 5-1 again. Therefore, access to a memory can be attained without coordinate between address registers and block registers.
COPYRIGHT: (C)1980,JPO&Japio
JP12432278A 1978-10-09 1978-10-09 Data processing system Pending JPS5552582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12432278A JPS5552582A (en) 1978-10-09 1978-10-09 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12432278A JPS5552582A (en) 1978-10-09 1978-10-09 Data processing system

Publications (1)

Publication Number Publication Date
JPS5552582A true JPS5552582A (en) 1980-04-17

Family

ID=14882458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12432278A Pending JPS5552582A (en) 1978-10-09 1978-10-09 Data processing system

Country Status (1)

Country Link
JP (1) JPS5552582A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62221057A (en) * 1986-03-06 1987-09-29 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Method and apparatus for generating pointer address
JPH0522344U (en) * 1991-09-05 1993-03-23 東洋紡績株式会社 Labeled container

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62221057A (en) * 1986-03-06 1987-09-29 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Method and apparatus for generating pointer address
JPH0522344U (en) * 1991-09-05 1993-03-23 東洋紡績株式会社 Labeled container

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