JPS54118139A - Information process control system - Google Patents

Information process control system

Info

Publication number
JPS54118139A
JPS54118139A JP2569378A JP2569378A JPS54118139A JP S54118139 A JPS54118139 A JP S54118139A JP 2569378 A JP2569378 A JP 2569378A JP 2569378 A JP2569378 A JP 2569378A JP S54118139 A JPS54118139 A JP S54118139A
Authority
JP
Japan
Prior art keywords
address
register group
information
main memory
attribute
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2569378A
Other languages
Japanese (ja)
Other versions
JPS5723950B2 (en
Inventor
Tsugio Miyake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2569378A priority Critical patent/JPS54118139A/en
Publication of JPS54118139A publication Critical patent/JPS54118139A/en
Publication of JPS5723950B2 publication Critical patent/JPS5723950B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To increase the processing speed with reduced quantity of the hardware for the intermediate information block storage device by indicating the proper storage device in the case of the new reference of the main memory.
CONSTITUTION: Intermediate memory unit 400 contains the 1st register group which stores the information within the main memory each in accordance with the attribute of the address referring to the information within main memory 200 from processor 100 plus the 2nd register group which stores the address within the main memory and of the information stored in the 1st register group. Thus, the address attribute signal showing the attribute of the information to be processed is given to the address. If the address coinciding with the address given from the processor existe in the 2nd register group, an access is given to the 1st register group; while these register groups are renewed in correspondence to the address attribute signal if not respectively.
COPYRIGHT: (C)1979,JPO&Japio
JP2569378A 1978-03-07 1978-03-07 Information process control system Granted JPS54118139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2569378A JPS54118139A (en) 1978-03-07 1978-03-07 Information process control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2569378A JPS54118139A (en) 1978-03-07 1978-03-07 Information process control system

Publications (2)

Publication Number Publication Date
JPS54118139A true JPS54118139A (en) 1979-09-13
JPS5723950B2 JPS5723950B2 (en) 1982-05-21

Family

ID=12172863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2569378A Granted JPS54118139A (en) 1978-03-07 1978-03-07 Information process control system

Country Status (1)

Country Link
JP (1) JPS54118139A (en)

Also Published As

Publication number Publication date
JPS5723950B2 (en) 1982-05-21

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