JPS5542446A - Fault detection/identification system - Google Patents
Fault detection/identification systemInfo
- Publication number
- JPS5542446A JPS5542446A JP11576378A JP11576378A JPS5542446A JP S5542446 A JPS5542446 A JP S5542446A JP 11576378 A JP11576378 A JP 11576378A JP 11576378 A JP11576378 A JP 11576378A JP S5542446 A JPS5542446 A JP S5542446A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- rank
- interface circuit
- call
- fault detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
- H04M3/241—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for stored program controlled exchanges
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Monitoring And Testing Of Exchanges (AREA)
- Exchange Systems With Centralized Control (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To carry out the fault detection and identification for the call system via the higher-rank processor by providing the inter-processor interface circuit between the higher-rank processor and the call-system interface circuit, thus ensuring execution of the control action for the resource switching and others. CONSTITUTION:Inter-processor interface circuit 9 is provided between processor 5 and call-system interface circuit 6 in the function dispersion type multi-processor system telephone exchange which contains higher-rank processor 5 performing the resource control and lower-rank processor 8 performing the direct control of call system 1. Thus a direct access is given to the fault information storage area of lower-rank processor memory 7 via the control command given from processor 5 to make possible the non-answer identification to the command of processor 5 at the abnormal time of processor 8 and its subsequent processors. Then the fault detection and identification is carried out for system 1 and processor 5 through circuit 6. In this way, the control action is carried out for the resource switching and others.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53115763A JPS5841537B2 (en) | 1978-09-22 | 1978-09-22 | Fault detection identification method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53115763A JPS5841537B2 (en) | 1978-09-22 | 1978-09-22 | Fault detection identification method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5542446A true JPS5542446A (en) | 1980-03-25 |
JPS5841537B2 JPS5841537B2 (en) | 1983-09-13 |
Family
ID=14670432
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53115763A Expired JPS5841537B2 (en) | 1978-09-22 | 1978-09-22 | Fault detection identification method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5841537B2 (en) |
-
1978
- 1978-09-22 JP JP53115763A patent/JPS5841537B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5841537B2 (en) | 1983-09-13 |
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