JPS551631A - Interrupt processing system - Google Patents

Interrupt processing system

Info

Publication number
JPS551631A
JPS551631A JP7434978A JP7434978A JPS551631A JP S551631 A JPS551631 A JP S551631A JP 7434978 A JP7434978 A JP 7434978A JP 7434978 A JP7434978 A JP 7434978A JP S551631 A JPS551631 A JP S551631A
Authority
JP
Japan
Prior art keywords
memory
bank
psw
register
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7434978A
Other languages
Japanese (ja)
Inventor
Kunio Murakami
Naohisa Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP7434978A priority Critical patent/JPS551631A/en
Publication of JPS551631A publication Critical patent/JPS551631A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To avoid the system down dependent upon the trouble of memory banks by using two memory banks respectively to double the save area for an executing PSW and an interrupt processing PSW and providing and doubling a memory trouble processing program in two memory banks.
CONSTITUTION: When a memory trouble is reported to CPU 14 through data path 15, contents of register 13 are stored in old PAW 7 through data path 15, control unit 21 and data path 16 if the faulty memory bank is other than memory banks 2 and 4, and new PSW 8 is stored in register 13, thereby executing a memory trouble processing program in memory bank 4. If the faulty memory bank is bank 2 or bank 4, contents of register 13 are stored in old PSW 9 through control unit 22, and new PSW 10 is stored in register 13, thereby executing a memory trouble processing program in memory bank 5.
COPYRIGHT: (C)1980,JPO&Japio
JP7434978A 1978-06-20 1978-06-20 Interrupt processing system Pending JPS551631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7434978A JPS551631A (en) 1978-06-20 1978-06-20 Interrupt processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7434978A JPS551631A (en) 1978-06-20 1978-06-20 Interrupt processing system

Publications (1)

Publication Number Publication Date
JPS551631A true JPS551631A (en) 1980-01-08

Family

ID=13544547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7434978A Pending JPS551631A (en) 1978-06-20 1978-06-20 Interrupt processing system

Country Status (1)

Country Link
JP (1) JPS551631A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4980936A (en) * 1972-12-11 1974-08-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4980936A (en) * 1972-12-11 1974-08-05

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