JPS57181489A - Information processor - Google Patents

Information processor

Info

Publication number
JPS57181489A
JPS57181489A JP56065635A JP6563581A JPS57181489A JP S57181489 A JPS57181489 A JP S57181489A JP 56065635 A JP56065635 A JP 56065635A JP 6563581 A JP6563581 A JP 6563581A JP S57181489 A JPS57181489 A JP S57181489A
Authority
JP
Japan
Prior art keywords
register
fix
computer
access
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56065635A
Other languages
Japanese (ja)
Inventor
Hajime Nakaya
Masahiro Kurata
Shizuo Shiokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56065635A priority Critical patent/JPS57181489A/en
Publication of JPS57181489A publication Critical patent/JPS57181489A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To reduce overhead, by returning the content of a status register to the initial value preceding to the access of a pre-fix area at the generation of designated event. CONSTITUTION:When a virtual computer 1 is run, a pre-fix register 12 is selected with the content of a status register 14 and the pre-fix conversion of a real address to a register 21 is made by using the register 12. If this real address is an address indicating the access to the pre-fix area, the pre-fix conversion is made and the access of the pre-fix area of the computer (i) is made. If an event such as interruption takes place at the operation of the computer (i), the register 14 is reset with a reception circuit 18 and returned to the initial value, allowing the switching to a pre-fix register 11. Further, a dispatcher sets the identification number of a virtual computer (j) running next to the register 14, the switching to the register 13 is made, and PSW for the computer (j) is loaded for execution.
JP56065635A 1981-04-30 1981-04-30 Information processor Pending JPS57181489A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56065635A JPS57181489A (en) 1981-04-30 1981-04-30 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56065635A JPS57181489A (en) 1981-04-30 1981-04-30 Information processor

Publications (1)

Publication Number Publication Date
JPS57181489A true JPS57181489A (en) 1982-11-08

Family

ID=13292673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56065635A Pending JPS57181489A (en) 1981-04-30 1981-04-30 Information processor

Country Status (1)

Country Link
JP (1) JPS57181489A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62117046A (en) * 1985-11-18 1987-05-28 Fujitsu Ltd Prefix control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62117046A (en) * 1985-11-18 1987-05-28 Fujitsu Ltd Prefix control system
JPH0450620B2 (en) * 1985-11-18 1992-08-14 Fujitsu Ltd

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