JPS5530866A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5530866A
JPS5530866A JP10452978A JP10452978A JPS5530866A JP S5530866 A JPS5530866 A JP S5530866A JP 10452978 A JP10452978 A JP 10452978A JP 10452978 A JP10452978 A JP 10452978A JP S5530866 A JPS5530866 A JP S5530866A
Authority
JP
Japan
Prior art keywords
drain
source
silicon substrate
channel cuts
dioxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10452978A
Other languages
Japanese (ja)
Inventor
Yoshikazu Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP10452978A priority Critical patent/JPS5530866A/en
Publication of JPS5530866A publication Critical patent/JPS5530866A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the integration degree and reduce the consumption of power of providing, as channel cuts, narrow but deep grooves in a silicon substrate by the plasma etching techniques.
CONSTITUTION: Over a silicon substrate 1 is formed a silicon dioxide layer 10. Mask patterns 4e and formed by the photo process method, which serve for impurity doping on source and drain. As a result of the doping, a source 2 and a drain 3 are obrained for substrate 1. In this case, the impurity doping is arranged so that source 2 and drain 3 individually are intersected with silicon dioxide layer 10 and channel cuts 12. Thereupon, a gate electrode 6, electrodes 7 and a passivated thin film 9 are formed, thus finally obtaining a transistor of the MOS type having grooves as channel cuts in the silicon substrate.
COPYRIGHT: (C)1980,JPO&Japio
JP10452978A 1978-08-28 1978-08-28 Semiconductor device Pending JPS5530866A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10452978A JPS5530866A (en) 1978-08-28 1978-08-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10452978A JPS5530866A (en) 1978-08-28 1978-08-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5530866A true JPS5530866A (en) 1980-03-04

Family

ID=14383010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10452978A Pending JPS5530866A (en) 1978-08-28 1978-08-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5530866A (en)

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