JPS5528565A - Memory system - Google Patents
Memory systemInfo
- Publication number
- JPS5528565A JPS5528565A JP10127978A JP10127978A JPS5528565A JP S5528565 A JPS5528565 A JP S5528565A JP 10127978 A JP10127978 A JP 10127978A JP 10127978 A JP10127978 A JP 10127978A JP S5528565 A JPS5528565 A JP S5528565A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- address
- auxiliary
- circuit
- terms
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To prevent the increment of the access time by providing the defective word display flag within the main memory and then growing the address of the auxiliary memory which performs substitution for the main memory via the test matrix in terms of the code logic.
CONSTITUTION: The arithmetic processor transmits the address information within register 1 to address decoder 2 of main memory 3 and address conversion circuit 5 via signal bus 12. Defective word display flag 4 is provided at part of memory 3. And auxiliary memory 8 performs substitution for memory 3 in case the word containing the defective bit exists in memory 3. Either memory 3 or 8 is selected by data serection circuit 10 to be taken into data buffer 11. The address of memory 8 is grown via the test matrix in terms of the code logic regarding to the address of memory 3. Furthermore, in case memory 8 contains some defect, the auxiliary memory address line is switched by connection/break circuit 21.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10127978A JPS5528565A (en) | 1978-08-19 | 1978-08-19 | Memory system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10127978A JPS5528565A (en) | 1978-08-19 | 1978-08-19 | Memory system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5528565A true JPS5528565A (en) | 1980-02-29 |
Family
ID=14296423
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10127978A Pending JPS5528565A (en) | 1978-08-19 | 1978-08-19 | Memory system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5528565A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008050455A1 (en) | 2006-10-27 | 2008-05-02 | Fujitsu Limited | Address line fault treating apparatus, address line fault treating method, address line fault treating program, information processing apparatus and memory controller |
-
1978
- 1978-08-19 JP JP10127978A patent/JPS5528565A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008050455A1 (en) | 2006-10-27 | 2008-05-02 | Fujitsu Limited | Address line fault treating apparatus, address line fault treating method, address line fault treating program, information processing apparatus and memory controller |
US7853838B2 (en) | 2006-10-27 | 2010-12-14 | Fujitsu Limited | Method and apparatus for handling failure in address line |
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