JPS5520515A - Encoder - Google Patents

Encoder

Info

Publication number
JPS5520515A
JPS5520515A JP9217178A JP9217178A JPS5520515A JP S5520515 A JPS5520515 A JP S5520515A JP 9217178 A JP9217178 A JP 9217178A JP 9217178 A JP9217178 A JP 9217178A JP S5520515 A JPS5520515 A JP S5520515A
Authority
JP
Japan
Prior art keywords
terminals
signal corresponding
full adder
binary signal
input terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9217178A
Other languages
Japanese (ja)
Other versions
JPS6019594B2 (en
Inventor
Hiroshi Yasuda
Yoshio Osakabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP53092171A priority Critical patent/JPS6019594B2/en
Publication of JPS5520515A publication Critical patent/JPS5520515A/en
Publication of JPS6019594B2 publication Critical patent/JPS6019594B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To establish the encoder simple in the circuit and low in cost, by using the full adder.
CONSTITUTION: Assuming that the m sets of inputs are encoded into the binary code in n-bit. This invention applies to M and n satisfying m/2≤n<m. Explanation is made to the case of m=8 and n=4, as the actual execution example. The input terminals A1 to A4 are connected to the output terminals C1 to C4 via the diodes D1 to D4, and the input terminals A5 to A8 are via the full adder 3 and the diodes D5 to D8. The binary signal corresponding to 5 in decimal system is fed to the terminals H1 to H4 of the full adder 3. When the switch SW selects one of the input terminals A1 to A4, the binary signal corresponding to 1,2,4,8 in decimal number is obtained at the output terminals C1 to C4 to the selection, and similarly the binary signal corresponding to 6,7,9,13 in decimal number is obtained when one of the terminals A5 to A8 is selected.
COPYRIGHT: (C)1980,JPO&Japio
JP53092171A 1978-07-28 1978-07-28 encoder Expired JPS6019594B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53092171A JPS6019594B2 (en) 1978-07-28 1978-07-28 encoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53092171A JPS6019594B2 (en) 1978-07-28 1978-07-28 encoder

Publications (2)

Publication Number Publication Date
JPS5520515A true JPS5520515A (en) 1980-02-14
JPS6019594B2 JPS6019594B2 (en) 1985-05-16

Family

ID=14046977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53092171A Expired JPS6019594B2 (en) 1978-07-28 1978-07-28 encoder

Country Status (1)

Country Link
JP (1) JPS6019594B2 (en)

Also Published As

Publication number Publication date
JPS6019594B2 (en) 1985-05-16

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