JPS577629A - Converting circuit - Google Patents
Converting circuitInfo
- Publication number
- JPS577629A JPS577629A JP8163880A JP8163880A JPS577629A JP S577629 A JPS577629 A JP S577629A JP 8163880 A JP8163880 A JP 8163880A JP 8163880 A JP8163880 A JP 8163880A JP S577629 A JPS577629 A JP S577629A
- Authority
- JP
- Japan
- Prior art keywords
- counting circuit
- digit
- decimal
- comparing
- numbers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
- H03M7/06—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two
- H03M7/08—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two the radix being ten, i.e. pure decimal code
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To prevent the scale of a converting circuit for binary-to-decimal conversion, etc., and its conversion time from increasing quickly even when the number of signal input terminals increases. CONSTITUTION:When a binary code 101110100111 is converted into a decimal number, 1+2+4+32+128+256+512+1048=2983 should be operated, but the addition of numbers of the low-order one digit is carried out by a comparing and counting circuit 1 and a counting circuit 9 shown at the right end of the figure, and a carry signal 14 is outputted to the 2nd counting circuit 9 from the left. Simultaneously, the 2nd comparing and counting circuit 1 and counting circuit 9 from the left are used to add the said carry signal 14 to the addition of only numbers of the 2nd digit from the least significant digit. Similarly, operations up to the most significant digit are performed and the decimal signal appears at the output 6 of the counting circuit 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8163880A JPS577629A (en) | 1980-06-17 | 1980-06-17 | Converting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8163880A JPS577629A (en) | 1980-06-17 | 1980-06-17 | Converting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS577629A true JPS577629A (en) | 1982-01-14 |
Family
ID=13751874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8163880A Pending JPS577629A (en) | 1980-06-17 | 1980-06-17 | Converting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS577629A (en) |
-
1980
- 1980-06-17 JP JP8163880A patent/JPS577629A/en active Pending
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