JPS54153544A - Peak hold circuit - Google Patents

Peak hold circuit

Info

Publication number
JPS54153544A
JPS54153544A JP6269778A JP6269778A JPS54153544A JP S54153544 A JPS54153544 A JP S54153544A JP 6269778 A JP6269778 A JP 6269778A JP 6269778 A JP6269778 A JP 6269778A JP S54153544 A JPS54153544 A JP S54153544A
Authority
JP
Japan
Prior art keywords
binary code
fed
latch circuit
code
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6269778A
Other languages
Japanese (ja)
Other versions
JPS6042559B2 (en
Inventor
Takeshi Kutaragi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP53062697A priority Critical patent/JPS6042559B2/en
Publication of JPS54153544A publication Critical patent/JPS54153544A/en
Publication of JPS6042559B2 publication Critical patent/JPS6042559B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE:To establish the peak hold circuit which converts the inputted analog value to binary code and holds the maximum or minimum value with the binary code. CONSTITUTION:The input analog value from the terminal 1 is fed to the A-D converter 10 to convert it into parallel binary code in 4-bit, and this binary code is fed to the latch circuit 20 while keeping parallel code. Further, the binary code from the latch circuit 20 and from the A-D converter 10 is respectively fed to the digiral comparator 30 while keeping parallel code, and it is detected which is greater out of the two binary codes. The detected output is fed to the latch circuit 20 as the control signal for the latch operation. The reset circuit is provided with the latch circuit 20. 50 is a switch for reset.
JP53062697A 1978-05-25 1978-05-25 Peak hold circuit Expired JPS6042559B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53062697A JPS6042559B2 (en) 1978-05-25 1978-05-25 Peak hold circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53062697A JPS6042559B2 (en) 1978-05-25 1978-05-25 Peak hold circuit

Publications (2)

Publication Number Publication Date
JPS54153544A true JPS54153544A (en) 1979-12-03
JPS6042559B2 JPS6042559B2 (en) 1985-09-24

Family

ID=13207736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53062697A Expired JPS6042559B2 (en) 1978-05-25 1978-05-25 Peak hold circuit

Country Status (1)

Country Link
JP (1) JPS6042559B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02259473A (en) * 1989-03-31 1990-10-22 Yokogawa Electric Corp Maximum value measuring circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02259473A (en) * 1989-03-31 1990-10-22 Yokogawa Electric Corp Maximum value measuring circuit

Also Published As

Publication number Publication date
JPS6042559B2 (en) 1985-09-24

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