JPS5582538A - Non-linear ad conversion circuit - Google Patents
Non-linear ad conversion circuitInfo
- Publication number
- JPS5582538A JPS5582538A JP15618178A JP15618178A JPS5582538A JP S5582538 A JPS5582538 A JP S5582538A JP 15618178 A JP15618178 A JP 15618178A JP 15618178 A JP15618178 A JP 15618178A JP S5582538 A JPS5582538 A JP S5582538A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- conversion
- signal
- gain
- sample hold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE: To simplify the circuit constitution, by discriminating whether the input analog signal is in excess of the compression level or not from a part of the output of A/D converter, and by selecting the gain of the variable gain circuit from the discrimination.
CONSTITUTION: In the initial condition, the switch SW of the variable gain control circuit 8 is connected to the contact b at low gain side. The sample hold circuit 2 is in sample hold condition with the control pulse SH from the timing pulse generating circuit 19, the analog input signal is attenuated for the level at the circuit 8 and inputted to the linear A/D conversion circuit 10 to perform A/D conversion. The decoder 20 discriminates whether or not the input analog signal f1 is to be compressed based on the output of upper rank 3-bit, and if the signal f1 is judged that it is not the level to be compressed at low amplitude, the A/D conversion instruction pulse CC is generated from the circuit 19 and the circuit 8 is made of a high gain by connecting SW to the contact a. Thus, the converter 10 performs A/D conversion for the signal in sample hold and outputs it from the higher digit bit sequentially.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15618178A JPS5582538A (en) | 1978-12-15 | 1978-12-15 | Non-linear ad conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15618178A JPS5582538A (en) | 1978-12-15 | 1978-12-15 | Non-linear ad conversion circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5582538A true JPS5582538A (en) | 1980-06-21 |
Family
ID=15622118
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15618178A Pending JPS5582538A (en) | 1978-12-15 | 1978-12-15 | Non-linear ad conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5582538A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57101420A (en) * | 1980-12-16 | 1982-06-24 | Fujitsu Ltd | Overflow detection system for analog-to-digital converter |
JPS58117708A (en) * | 1982-01-05 | 1983-07-13 | Yokogawa Hokushin Electric Corp | Automatic range setting device |
JPS5986328A (en) * | 1982-11-08 | 1984-05-18 | Fujitsu Ltd | Analog-digital converter |
-
1978
- 1978-12-15 JP JP15618178A patent/JPS5582538A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57101420A (en) * | 1980-12-16 | 1982-06-24 | Fujitsu Ltd | Overflow detection system for analog-to-digital converter |
JPS6159570B2 (en) * | 1980-12-16 | 1986-12-17 | Fujitsu Ltd | |
JPS58117708A (en) * | 1982-01-05 | 1983-07-13 | Yokogawa Hokushin Electric Corp | Automatic range setting device |
JPS5986328A (en) * | 1982-11-08 | 1984-05-18 | Fujitsu Ltd | Analog-digital converter |
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