JPS5489557A - Stabilizing circuit for analog digital converter - Google Patents

Stabilizing circuit for analog digital converter

Info

Publication number
JPS5489557A
JPS5489557A JP15989077A JP15989077A JPS5489557A JP S5489557 A JPS5489557 A JP S5489557A JP 15989077 A JP15989077 A JP 15989077A JP 15989077 A JP15989077 A JP 15989077A JP S5489557 A JPS5489557 A JP S5489557A
Authority
JP
Japan
Prior art keywords
analog input
input signal
level
digital converter
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15989077A
Other languages
Japanese (ja)
Inventor
Kenjiro Endo
Masanori Tanaka
Yoshiyuki Ishizawa
Koji Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
EMI Records Japan Inc
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Toshiba Emi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd, Toshiba Emi Ltd filed Critical Toshiba Corp
Priority to JP15989077A priority Critical patent/JPS5489557A/en
Publication of JPS5489557A publication Critical patent/JPS5489557A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To always perform stable digital signal conversion, by preventing the malfunction due to level variation or noise in advance through the constitution that if analog input signal does not change by a given level or more, the conversion operation is not performed.
CONSTITUTION: The sample hold circuit 12 sampling and holding the analog input signal Xi, level shift circuit 13 obtaining the upper and lower limits X+ and X- with the addition of a given increment, and comparison circuit 14 comparing the analog input signal Xi with the upper limit X+ and the lower limit X- for the level, are provided. As the result of comparison, if Xi>X+ or Xi<X-, the A/D converter 11 converts analog input signal into digital signal with the operation of the output of the comparison circuit 14 and it stops the converting operation, if X-< Xi<X+.
COPYRIGHT: (C)1979,JPO&Japio
JP15989077A 1977-12-27 1977-12-27 Stabilizing circuit for analog digital converter Pending JPS5489557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15989077A JPS5489557A (en) 1977-12-27 1977-12-27 Stabilizing circuit for analog digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15989077A JPS5489557A (en) 1977-12-27 1977-12-27 Stabilizing circuit for analog digital converter

Publications (1)

Publication Number Publication Date
JPS5489557A true JPS5489557A (en) 1979-07-16

Family

ID=15703405

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15989077A Pending JPS5489557A (en) 1977-12-27 1977-12-27 Stabilizing circuit for analog digital converter

Country Status (1)

Country Link
JP (1) JPS5489557A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56120219A (en) * 1980-02-27 1981-09-21 Matsushita Electric Ind Co Ltd Analog and digital conversion system
JP2006135436A (en) * 2004-11-02 2006-05-25 Fujitsu Ltd Analog/digital conversion method and circuit thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56120219A (en) * 1980-02-27 1981-09-21 Matsushita Electric Ind Co Ltd Analog and digital conversion system
JPS6137811B2 (en) * 1980-02-27 1986-08-26 Matsushita Electric Ind Co Ltd
JP2006135436A (en) * 2004-11-02 2006-05-25 Fujitsu Ltd Analog/digital conversion method and circuit thereof
JP4647284B2 (en) * 2004-11-02 2011-03-09 富士通セミコンダクター株式会社 Analog / digital conversion method and analog / digital conversion circuit

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