JPS55143450A - Digital mean value detector - Google Patents

Digital mean value detector

Info

Publication number
JPS55143450A
JPS55143450A JP11785678A JP11785678A JPS55143450A JP S55143450 A JPS55143450 A JP S55143450A JP 11785678 A JP11785678 A JP 11785678A JP 11785678 A JP11785678 A JP 11785678A JP S55143450 A JPS55143450 A JP S55143450A
Authority
JP
Japan
Prior art keywords
mean value
signal
memory
circuit
sampling period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11785678A
Other languages
Japanese (ja)
Inventor
Noboru Azusawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11785678A priority Critical patent/JPS55143450A/en
Publication of JPS55143450A publication Critical patent/JPS55143450A/en
Pending legal-status Critical Current

Links

Landscapes

  • Measurement Of Current Or Voltage (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

PURPOSE: To quicken response by obtaining a mean value by sampling an input signal, by storing the integral value of the input signal in a memory circuit by shifting by one sampling period, and by sequentially outputting stored values in the memory circuit.
CONSTITUTION: By a timing signal supplied to timing circuit TIM, the analog output signal of sample holding circuit SH is converted by A-D converter AD into a digital value and after the conversion, an end signal is output to timing circuit TIM. Integral values of the equally-divided signal are added to the contents of memory circuits M1WM8, provided as many as (n), being shifted by one sampling period respectively and memory values of memory circuits M1WM8 added as many as (n) at every sampling period are sequentially output so as to obtain the mean value.
COPYRIGHT: (C)1980,JPO&Japio
JP11785678A 1978-09-27 1978-09-27 Digital mean value detector Pending JPS55143450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11785678A JPS55143450A (en) 1978-09-27 1978-09-27 Digital mean value detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11785678A JPS55143450A (en) 1978-09-27 1978-09-27 Digital mean value detector

Publications (1)

Publication Number Publication Date
JPS55143450A true JPS55143450A (en) 1980-11-08

Family

ID=14721978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11785678A Pending JPS55143450A (en) 1978-09-27 1978-09-27 Digital mean value detector

Country Status (1)

Country Link
JP (1) JPS55143450A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58157680A (en) * 1982-03-09 1983-09-19 三菱電機株式会社 Controller for speed of elevator
JP2006204056A (en) * 2005-01-24 2006-08-03 Lecip Corp Charging method, charging device, and computer program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58157680A (en) * 1982-03-09 1983-09-19 三菱電機株式会社 Controller for speed of elevator
JP2006204056A (en) * 2005-01-24 2006-08-03 Lecip Corp Charging method, charging device, and computer program

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