JPS6137811B2 - - Google Patents
Info
- Publication number
- JPS6137811B2 JPS6137811B2 JP55023908A JP2390880A JPS6137811B2 JP S6137811 B2 JPS6137811 B2 JP S6137811B2 JP 55023908 A JP55023908 A JP 55023908A JP 2390880 A JP2390880 A JP 2390880A JP S6137811 B2 JPS6137811 B2 JP S6137811B2
- Authority
- JP
- Japan
- Prior art keywords
- analog
- amax
- pulse width
- signal
- digital conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0845—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of power supply variations, e.g. ripple
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】
本発明はマルチチヤンネルアナログ・パルス巾
変換器を用いたアナログ・デイジタル変換方式に
関するもので雑音に影響されることなく合理的に
アナログ・デイジタル変換できるようにしたもの
である。[Detailed Description of the Invention] The present invention relates to an analog-to-digital conversion method using a multi-channel analog-to-pulse width converter, which enables rational analog-to-digital conversion without being affected by noise. .
マルチチヤンネルアナログ・パルス巾変換器を
用いて複数のアナログ信号レベルをデイジタル変
換する場合、信号によつてその変換精度を変更し
たい時がある。（たとえば自動車のエンジン制御
装置における空気量、バツテリ電圧、水温等のア
ナログ量をデイジタル変換するにあたつて空気量
は10ビツト、バツテリ電圧、水温は８ビツトとい
うように）
今、３種のアナログ信号ＳA，ＳB，ＳCのうち
ＳA………10ビツト
ＳB………８ビツト
ＳC………８ビツト
とし、これをデイジタル信号に変換するにあたつ
て変換器入力端子におけるＳAの最大レベルＶAMA
Ｘに対して、ＳB，ＳCの最大レベルはＶAMAX／４
となるように設定し、入力レベルがＶAMAX／４の
時出力パルス巾が255×ＴC（ＴC……パルス巾計
数に用いるクロツク信号ＳCの周期）となるよう
に変換器の変換感度を設定することにより可能で
ある。 When converting a plurality of analog signal levels to digital using a multichannel analog pulse width converter, there are times when it is desired to change the conversion accuracy depending on the signal. (For example, when converting analog quantities such as air volume, battery voltage, and water temperature in a car engine control system into digital, the air volume is 10 bits, and the battery voltage and water temperature are 8 bits.) Currently, there are three types of analogs. Of the signals S A , S B , and S C , S A ...... 10 bits S B ...... 8 bits S C ...... 8 bits, and when converting these into digital signals, at the converter input terminal Maximum level of S A V AMA
For X , the maximum level of S B and S C is V AMAX /4
The conversion sensitivity of the converter is set so that when the input level is V AMAX /4, the output pulse width is 255 x T C (TC...period of the clock signal S C used for pulse width counting ) . This is possible by setting .
しかしＶAMAXを変換器の変換の直線性が保たれ
る入力範囲内に設定するとＳB，ＳCの入力レベル
が小さくなり電源ライン、アースライン等に重畳
した雑音の影響を受けやすくなる。 However, if V AMAX is set within the input range that maintains the linearity of the converter's conversion, the input levels of S B and S C become small, making them susceptible to noise superimposed on the power supply line, earth line, etc.
今、ＳB，ＳCの入力レベルを大きくするとＳA
の入力レベルの最大値附近（ＶAMAX）で変換器
の直線性が失なわれてしまう。 Now, if we increase the input levels of S B and S C , S A
The linearity of the converter is lost near the maximum value of the input level (V AMAX ).
さらにＳAの変換に時間がかかる。（ＳAの最大
変換時間はＳB，ＳCの最大変換時間の４倍）
本発明はこれらの欠点を除去したものでアナロ
グ信号ＳA，ＳB，ＳCにおいて、ＳA（最大レベル
……ＶAMAX）を変換器の１つの入力端子に入力す
ると同時にこれを1/4に分圧した信号ＳA′（最大
レベル…ＶＡＭＡＸ／４）を他の入力端子に入力し、信
号
ＳA′によるパルス巾ＷA′が255/4×ＴC≒63TC′以
下か否かを判定し、63TC′以下の時にはＳAによ
るパルス巾ＷAをクロツクＳCを用いて計数した値
ＭA，63TC′を越える時にはＳA′によるパルス巾
ＷA′をクロツクＳCを用いて計数した値ＭA′の４
倍（すなわち4MA′）をそれぞれデイジタル変換
値とするようにしている。 Furthermore, it takes time to convert S A. (The maximum conversion time of S A is four times the maximum conversion time of S B and SC .) The present invention eliminates these drawbacks, and the maximum level of S A (maximum level ... ...V AMAX ) is input to one input terminal of the converter, and at the same time, a signal S A ' (maximum level ... V AMAX /4), which is divided to 1/4, is input to the other input terminal, and the signal S A It is determined whether the pulse width W A ′ due to S A is less than 255/4×T C ≒63T C ′, and if it is less than 63T C ′, the value M calculated by counting the pulse width W A due to S A using clock S C is determined. A , 63T C ′ is exceeded, the pulse width W A ′ due to S A ′ is counted using the clock S C 4 of M A ′
The multiplication (that is, 4M A ′) is set as a digital conversion value.
したがつてＳAはそのレベルが０〜ＶＡＭＡＸ／４の
範
囲の場合のみ信号ＳAによるパルスＷAはアナロ
グ・デイジタル変換に用いられ、ＶＡＭＡＸ／４を越え
る
場合はＳAのレベル1/4に分圧した信号ＳA′による
パルスＷA′がアナログ・デイジタル変換に用いら
れることになり、ＳB，ＳCおよびＳA′の最大値
ＶＡＭＡＸ／４を変換器の直線性が保たれる上限近くに
設
定でき、電源ライン等の雑音の影響を受けにくく
なると同時にデイジタル変換精度は最も高精度の
変換が必要なＳAが０〜ＶＡＭＡＸ／４の範囲内で10ビ
ツ
ト精度でとれる。またＶAMAX／４〜ＶAMAXの範囲
では８ビツトのアナログ・デイジタル変換になる
有効ビツト長を６ビツト以上にとれることにな
る。さらにＳAの入力レベルＶＡＭＡＸ／４以上の場合
必
要以上に高精度なデイジタル変換をおこなうため
に長い変換時間をかける必要がない。 Therefore, the pulse W A by the signal S A is used for analog-to-digital conversion only when the level of S A is in the range of 0 to V AMAX /4, and when it exceeds V AMAX /4, the level of S A is 1/4. The pulse W A ' resulting from the signal S A ' divided into 4 is used for analog-to-digital conversion, and the maximum value V AMAX /4 of S B , S C and S A ' is maintained to maintain the linearity of the converter. It can be set close to the upper limit of the voltage drop, making it less susceptible to noise from power lines, etc., and at the same time, digital conversion accuracy can be achieved with 10-bit accuracy within the range of 0 to V AMAX /4 for S A , which requires the most accurate conversion. . Further, in the range of V AMAX /4 to V AMAX , the effective bit length for 8-bit analog-to-digital conversion can be 6 bits or more. Furthermore, when the input level of S A is V AMAX /4 or higher, it is not necessary to take a long conversion time to perform digital conversion with higher precision than necessary.
第１図はアナログ・パルス巾変換器５０とアナ
ログ入力ＳA，ＳB，ＳC，ＳA′，ＳAよりＳA′を作
る手段５１、チヤンネル選択信号ライン５２、変
換開始信号ライン５３、出力ライン５４、ゲート
５５の関係を示す本発明の一実施例であつて、第
２図の助けをかりれば出力ライン５４への出力
〔ゲート５５の出力〕はチヤンネル選択信号ライ
ン５２からの信号によりチヤンネルを選択した状
態で変換開始信号ライン５３に加わる信号でゲー
ト５５が開かれた段階から変換器５０の出力が得
られる。第３図は従来のものとを比較してあらわ
したものでａ，ｃが従来のもの、ｂ，ｄが本発明
のものであつて、ａ，ｂの場合はＳAのレベル…
ＶAMAX，ＳB，ＳCのレベル…ＶＡＭＡＸ／４の状態を示
す。ｃ，ｄの場合はＳA，ＳB，ＳCのレベル…
ＶＡＭＡＸ／４の状態を示す。 FIG. 1 shows an analog pulse width converter 50, means 51 for generating S A ' from analog inputs S A , S B , S C , S A ', and S A , a channel selection signal line 52 , a conversion start signal line 53 , This is an embodiment of the present invention showing the relationship between the output line 54 and the gate 55. With the help of FIG. The output of the converter 50 is obtained from the stage when the gate 55 is opened by a signal applied to the conversion start signal line 53 with the channel selected. Figure 3 shows a comparison between the conventional model and the conventional model, where a and c are the conventional model, b and d are the inventive model, and in the case of a and b, the S A level...
The levels of V AMAX , S B , and S C indicate the state of V AMAX /4. In the case of c and d, the levels of S A , S B , and S C ...
Indicates the state of V AMAX /4.
以上実施例により説明したが本発明によればた
とえば自動車用エンジン制御装置等アナログ・デ
イジタル変換時間に制限があり、さらに部分的に
高精度なＡ／Ｄ変換が必要な場合特に有効であ
る。 As described above with reference to the embodiments, the present invention is particularly effective in cases where analog-to-digital conversion time is limited and high-precision A/D conversion is required, such as in an automobile engine control system.
第１図は本発明の一実施例におけるアナログ・
デイジタル変換方式のブロツク図、第２図はその
動作を示す波形図、第３図は従来の方法と本発明
の方法とによるアナログ信号をデイジタル巾信号
に変換した状態を比較して示す図である。
５０……アナログ・パルス巾変換器。
FIG. 1 shows an analog signal in one embodiment of the present invention.
A block diagram of the digital conversion method, FIG. 2 is a waveform diagram showing its operation, and FIG. 3 is a diagram comparing the state of converting an analog signal into a digital width signal by the conventional method and the method of the present invention. . 50...Analog pulse width converter.
Claims (1)
アナログ・パルス巾変換器における一つの入力端
子に入力させる一方、その信号ＳAのレベルを
１／Ｎ（Ｎ…整数）に分割した信号ＳA′を他の入
力端子に入力させ、上記ＳAのレベルがＶＡＭＡＸ／Ｎ
以 下の時はＳAに相当するパルス巾ＷA中のクロツク
数、ＶＡＭＡＸ／Ｎを越える時はＳA′に相当するパル
ス巾 ＷA′中のクロツク数のＮ倍をデイジタル変換値と
したことを特徴とするアナログ・デイジタル変換
方式。 ２ アナログ信号ＳAのＶＡＭＡＸ／Ｎはアナログ・パ
ル ス巾変換器に加わる他のアナログ信号ＳB，ＳCの
最大レベルと同等に設定したことを特徴とする特
許請求の範囲第１項記載のアナログ・デイジタル
変換方式。[Claims] 1. An analog signal S A whose maximum level is V AMAX is input to one input terminal of an analog pulse width converter, while the level of the signal S A is set to 1/N (N...an integer). The divided signal S A ' is inputted to another input terminal, and the level of the above S A is V AMAX /N
In the following cases, the number of clocks in the pulse width W A corresponding to S A is used, and when it exceeds V AMAX /N, the number of clocks in the pulse width W A ' corresponding to S A ' is N times the digital conversion value. An analog-to-digital conversion method characterized by: 2. The device according to claim 1, characterized in that V AMAX /N of the analog signal S A is set equal to the maximum level of the other analog signals S B and S C applied to the analog pulse width converter. Analog/digital conversion method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2390880A JPS56120219A (en) | 1980-02-27 | 1980-02-27 | Analog and digital conversion system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2390880A JPS56120219A (en) | 1980-02-27 | 1980-02-27 | Analog and digital conversion system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56120219A JPS56120219A (en) | 1981-09-21 |
| JPS6137811B2 true JPS6137811B2 (en) | 1986-08-26 |
Family
ID=12123573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2390880A Granted JPS56120219A (en) | 1980-02-27 | 1980-02-27 | Analog and digital conversion system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56120219A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5489557A (en) * | 1977-12-27 | 1979-07-16 | Toshiba Corp | Stabilizing circuit for analog digital converter |
-
1980
- 1980-02-27 JP JP2390880A patent/JPS56120219A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5489557A (en) * | 1977-12-27 | 1979-07-16 | Toshiba Corp | Stabilizing circuit for analog digital converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56120219A (en) | 1981-09-21 |
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