JPS5668831A - Decoding circuit - Google Patents

Decoding circuit

Info

Publication number
JPS5668831A
JPS5668831A JP14521179A JP14521179A JPS5668831A JP S5668831 A JPS5668831 A JP S5668831A JP 14521179 A JP14521179 A JP 14521179A JP 14521179 A JP14521179 A JP 14521179A JP S5668831 A JPS5668831 A JP S5668831A
Authority
JP
Japan
Prior art keywords
decoder
types
decoding
decoders
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14521179A
Other languages
Japanese (ja)
Inventor
Hisanori Hamano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14521179A priority Critical patent/JPS5668831A/en
Publication of JPS5668831A publication Critical patent/JPS5668831A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To obtain the decoding output signals of 2n+1 types or more out of the input signals of (n) bits, by actuating selectively one of the (m) units of decoders according to the state of the FF in the instruction decoding circuit of a microprocessor or the like.
CONSTITUTION: The 1st decoder 2a is put under the active state, and the 2nd decoder 2b is put under the inactive state respectively. Thus the instruction code to be supplied is decoded at the decoder 2a, and the decoding signal corresponding to the instruction code is delivered from the output end. When the decoder 2b is actuated, the instruction codes to be subsequently supplied are decoded by the decoder 2b to deliver the output signal corresponding to the instruction code through the output end. In this case, the outputs of 2×(2n-1) types in all are obtained from the decoders 2a and 2b by 2n-1 types each. And in general, the decoding output signals of 2n+1 types or more can be obtained from the input signals of (n) bits in the case of decoders of (m) units.
COPYRIGHT: (C)1981,JPO&Japio
JP14521179A 1979-11-08 1979-11-08 Decoding circuit Pending JPS5668831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14521179A JPS5668831A (en) 1979-11-08 1979-11-08 Decoding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14521179A JPS5668831A (en) 1979-11-08 1979-11-08 Decoding circuit

Publications (1)

Publication Number Publication Date
JPS5668831A true JPS5668831A (en) 1981-06-09

Family

ID=15379941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14521179A Pending JPS5668831A (en) 1979-11-08 1979-11-08 Decoding circuit

Country Status (1)

Country Link
JP (1) JPS5668831A (en)

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