JPS6019594B2 - encoder - Google Patents

Description

Detailed Description of the Invention The present invention has a plurality of input terminals and a plurality of output terminals smaller than the number of input terminals, and a signal is supplied to any one of the plurality of input terminals. The present invention relates to an improvement of an encoder in which a binary encoded signal having the number of bits corresponding to the number of output terminals is outputted to a plurality of output terminals according to the number of output terminals.

First, a conventional encoder of this type will be explained with reference to FIG.

In FIG. 1, A, ~A8 are eight input terminals,
At the same time, these become the fixed contacts of the changeover switch SW, and from the movable contact B, the DC voltage from the DC power source E is selectively supplied as a signal to any one of these input terminals A, ~A8, and these input terminals A, ~A8 is supplied to a 4-bit binary encoder 1, and its output terminals C, ~C4
A 4-bit binary encoded signal is output at each time. This 4-bit binary encoded signal is then supplied as an address signal to a circuit 2 having an address such as a memory. In Fig. 1, the output signals of the output terminals C, ~C4 are designated as S, ~S4, the switch positions of the changeover switch SW are designated as A, ~A8, and the corresponding 4-bit binary encoded signals are 1 and 18 respectively, the binary encoded signal 1 corresponding to each of these switch positions will be as shown in the truth table of FIG.

However, such a binary encoder has the disadvantage that its circuit is complicated and expensive.

In view of these points, the present invention aims to propose an encoder of this type which has a simple circuit and is inexpensive, without using a binary encoder which has a complicated circuit and is expensive. The present invention has m input terminals A,, A2..., Am and n output terminals C., C2 (n<n<m).
-, Cn, and m output terminals A,, A2...
. . . n output terminals C, , C2 . . . depending on which one input terminal of Am is supplied with the signal.
・In an encoder that outputs an n-bit binary encoded signal to Cn, the inputs of n input terminals A,, A2, . . ., An out of m input terminals are are supplied to n output terminals C,, C2..., Cn, respectively, and among m input terminals A,,..., An, (
m-n) input terminals An1, An+2, ..., Am
After supplying the input to a full adder and adding it with a predetermined n-bit binary encoded signal, n output terminals C,, C2, . . .
..., Cn.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a Z diagram showing the embodiment of the present invention as a whole, and A, to A8 are eight input terminals. These input terminals A, -A8 simultaneously serve as fixed contacts of a changeover switch SW, to which a DC voltage from a DC power source E is selectively supplied as a signal from their movable contacts B. C, ~C4 are Z4 output terminals, and these output terminals C, ~C4 are a circuit 2 having an address of a memory, etc.
It is connected to the. Input terminals A, ~A4 are connected to output terminals C, ~C4, respectively, through buffer diodes D, ~D4, respectively. Further, the output terminals C, .about.C4 are grounded through load resistors R, .about.R4, respectively. Input terminal A
5 to & are connected to input terminals G, to G4 of the full adder 3. The other input terminals of the full adder 3 are "010".
1'' (corresponding to the number 5 of 1) is supplied. Therefore, the DC voltage from the DC power supply E is connected to the input terminals 1 and 3 via the terminal F, and the grounded terminal F2 is connected to the input terminals & and 4. J. ~J4 is the output terminal of the full adder 3, and the input terminal G,, day,; G2, day 2: G3, day 3
The binary encoded signals of three bits supplied to G4 and Day 4 are respectively added, and the summed outputs are obtained at the output terminals J, , J2, J3 and J4, respectively. full adder J
,~J4 outputs are buffer diodes D5~D6, respectively.
It is connected to the output terminals C and C4 through the terminals C and C4.
3 In this case, a gate (not shown) that provides an addition output to the output terminals J, ~J4 only when the movable contact B of the changeover switch SW is connected to the fixed contacts (input terminals) A5 ~ A8 is connected to the full addition gate (not shown). It is provided inside the container 3.
A more specific configuration of the 4-full adder 3 is shown in FIG. This full adder 3 consists of full adders (3-1) to (3-4) for each digit of 1 bit, and is configured so that each carryout signal is supplied to the next stage full adder. There is. Further, a specific configuration of the full adder for each bit in FIG. 4 is shown in FIG. 5.

G and each input terminal G in Fig. 3 and Fig. 4, ~
○4 and day, .about.ratio are shown as representatives, and similarly, J is also shown as a representative of each output terminal J, .about.J4. Further, CI is a carry-in terminal, and CO is a carry-out terminal. The input of the input terminal G is supplied to the AND circuit 4 and the /A circuit 5, and the input of the other input terminal G is supplied to the AND circuit 4 and the NOR circuit 5. The output of the AND circuit 4 is supplied to the NOR circuit 6 and also to the OR circuit 9. The output of the /A circuit 5 is supplied to a NOR circuit 6, and is also supplied to an AND circuit 8 after having its phase inverted. The output of the NOR circuit 6 is supplied to an exclusive OR circuit 7. The carry-in signal from the carry-in terminal CI is sent to the exclusive OR circuit 7.
and is supplied to the AND circuit 8. The output of exclusive OR circuit 7 is output to output terminal J. The output of the AND circuit 8 is supplied to an OR circuit 9. The output of the OR circuit 9 is output to the carry-out terminal GO. Next, the operation of the encoder of the embodiment shown in FIG. 3 will be explained with reference to the truth table shown in FIG. 6, which corresponds to FIG. 2.

In FIG. 6, the binary encoded signals obtained at the output terminals C, .about.C4 are shown as 1', and the binary encoded signals at the respective switch positions A, .about.R8 are shown as 1', .about.r8. Further, a predetermined binary encoded signal supplied to the full adder 3 from the input terminals F and F2 is indicated as lo. When the switch position is A, ~, 2 is obtained at output terminal C, ~C4.
The hexadecimal encoded signals 1' to 1'4 are binary encoded signals corresponding to decimal numbers 1, 2, 4, and 8, as shown in FIG.

Also, since the predetermined binary encoded signal supplied to the full adder 3 from the input terminals F and F2 is "0101" in this example, that is, 5 if converted into decimal, the switch position is &~A.
The binary encoded outputs r5 to 1'8 obtained in the output states C and .about.C4 of 8 are the outputs obtained by adding lo to r and .about.r4, respectively. In the above embodiment, m mentioned at the beginning is 8, and n
This is the case where the average is 4.

When it is equal to the simulated number M, the predetermined binary encoded signal lo
must be a value less than or equal to 2n-1-1 when converted into a decimal number, but this restriction does not necessarily apply when m is smaller than 0.

In short, it is predetermined so that different n-bit binary encoded signals are output to n output terminals depending on which one of the m input terminals is supplied with a signal. What is necessary is to determine the value of the binary encoded signal. According to the present invention described above, the circuit structure is simple and inexpensive, and it has a plurality of input terminals and a plurality of output terminals whose number is smaller than the number of input terminals, and which one of the input terminals is input. It is possible to obtain an esocoder that outputs a binary encoded signal having a number of bits corresponding to the number of output terminals to a plurality of output terminals depending on whether a signal is supplied to the terminal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional encoder, FIG. 2 is a truth table for explaining FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a block diagram showing a conventional encoder. 5 is a block diagram showing a part of FIG. 3, FIG. 5 is a circuit diagram showing a part of FIG. 4, and FIG. 6 is a truth table for explaining FIG. OA, - are input terminals, C, -C4 are output terminals, and 3 is a full adder. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 m input terminals A_1, A_2..., Am and n output terminals C_1, C_2..., C (m/2≦n<m)
n, and the m input terminals A_1, A_2...,
The n output terminals C_1, C_2..., C depend on which one input terminal of Am is supplied with the signal.
In an encoder configured to output an n-bit binary encoded signal to n, the inputs of n input terminals A_1, A_2..., An among the m input terminals are respectively connected to n.
output terminals C_1, C_2..., Cn, and the remaining (m-n) input terminals A_n_+_1, A_n_+ among the m input terminals A_1, A_2..., Am.
The inputs of _2, . Featured encoder.