JPS55163876A - Charge coupled device and manufacture thereof - Google Patents

Charge coupled device and manufacture thereof

Info

Publication number
JPS55163876A
JPS55163876A JP7201779A JP7201779A JPS55163876A JP S55163876 A JPS55163876 A JP S55163876A JP 7201779 A JP7201779 A JP 7201779A JP 7201779 A JP7201779 A JP 7201779A JP S55163876 A JPS55163876 A JP S55163876A
Authority
JP
Japan
Prior art keywords
channel
region
layer
potential barrier
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7201779A
Other languages
Japanese (ja)
Other versions
JPS6325511B2 (en
Inventor
Hiroo Wakaumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7201779A priority Critical patent/JPS55163876A/en
Publication of JPS55163876A publication Critical patent/JPS55163876A/en
Publication of JPS6325511B2 publication Critical patent/JPS6325511B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823406Combination of charge coupled devices, i.e. CCD, or BBD

Abstract

PURPOSE:To improve the dynamic range of a charge coupled device by forming a potential barrier region between a channel and a field region to reduce a dark current. CONSTITUTION:A gate electrode 13 is formed through a gate oxide film 12' on a substrate 11, and a potential well 32' is formed in the channel region 15 directly under the electrode 13. A high impurity density layer 50 is formed around an active channel region 15 in contact with an impurity layer 14 and a channel region 15. When the impurity density of the layer 50 is increased higher in distribution than the density of the channel stopping layer 14, a potential barrier 33 is formed. The charge thermally generated in the field region is prevented from flowing into the channel due to the potential barrier, it can prevent the decrease of the dynamic range of the charge due to dark current.
JP7201779A 1979-06-08 1979-06-08 Charge coupled device and manufacture thereof Granted JPS55163876A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7201779A JPS55163876A (en) 1979-06-08 1979-06-08 Charge coupled device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7201779A JPS55163876A (en) 1979-06-08 1979-06-08 Charge coupled device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS55163876A true JPS55163876A (en) 1980-12-20
JPS6325511B2 JPS6325511B2 (en) 1988-05-25

Family

ID=13477215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7201779A Granted JPS55163876A (en) 1979-06-08 1979-06-08 Charge coupled device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS55163876A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54102982A (en) * 1978-01-31 1979-08-13 Mitsubishi Electric Corp Charge transfer type semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54102982A (en) * 1978-01-31 1979-08-13 Mitsubishi Electric Corp Charge transfer type semiconductor device

Also Published As

Publication number Publication date
JPS6325511B2 (en) 1988-05-25

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