JPS55141749A - Dynamic memory cell - Google Patents

Dynamic memory cell

Info

Publication number
JPS55141749A
JPS55141749A JP4980779A JP4980779A JPS55141749A JP S55141749 A JPS55141749 A JP S55141749A JP 4980779 A JP4980779 A JP 4980779A JP 4980779 A JP4980779 A JP 4980779A JP S55141749 A JPS55141749 A JP S55141749A
Authority
JP
Japan
Prior art keywords
layer
memory cell
film
dynamic memory
depletion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4980779A
Other languages
Japanese (ja)
Inventor
Kunimitsu Fujiki
Toshihiro Sekikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI, Agency of Industrial Science and Technology filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP4980779A priority Critical patent/JPS55141749A/en
Publication of JPS55141749A publication Critical patent/JPS55141749A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

PURPOSE:To improve the integrity of a dynamic memory cell by controlling depletion layers formed in two semiconductor layers by a set voltage and forming the dynamic memory cell requiring no switching transistor by utilizing the punch through phenomenon of the depletion layers. CONSTITUTION:There are formed an n<+>-type impurity layer 102 becoming a bit line on one surface of a p-type silicon layer 101, and an insulating film 104 made of a thin oxide film capable of forming a channel (inversion layer) 103 becoming one electrode of a capacitor on the other surface of the layer 101. Further, there is also formed a conductive film 105 becoming a word line and the other electrode of the capacitor on the film 104. It is controllable by the voltage value applied to the film 105 whether a punch through phenomenon between a depletion layer formed in the layer 101 and a depletion layer formed in the layer 101 upon application of a voltage to the layer 102 may occur or not.
JP4980779A 1979-04-24 1979-04-24 Dynamic memory cell Pending JPS55141749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4980779A JPS55141749A (en) 1979-04-24 1979-04-24 Dynamic memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4980779A JPS55141749A (en) 1979-04-24 1979-04-24 Dynamic memory cell

Publications (1)

Publication Number Publication Date
JPS55141749A true JPS55141749A (en) 1980-11-05

Family

ID=12841396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4980779A Pending JPS55141749A (en) 1979-04-24 1979-04-24 Dynamic memory cell

Country Status (1)

Country Link
JP (1) JPS55141749A (en)

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE JOURNAL OF SOLID-STATE=1976 *
IEEE JOURNAL OF SOLID-STATE=1977 *

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