JPS55134595A - Memory switch circuit - Google Patents

Memory switch circuit

Info

Publication number
JPS55134595A
JPS55134595A JP4177779A JP4177779A JPS55134595A JP S55134595 A JPS55134595 A JP S55134595A JP 4177779 A JP4177779 A JP 4177779A JP 4177779 A JP4177779 A JP 4177779A JP S55134595 A JPS55134595 A JP S55134595A
Authority
JP
Japan
Prior art keywords
memories
speed
low
channel
common line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4177779A
Other languages
English (en)
Japanese (ja)
Other versions
JPS625399B2 (enrdf_load_stackoverflow
Inventor
Takao Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4177779A priority Critical patent/JPS55134595A/ja
Publication of JPS55134595A publication Critical patent/JPS55134595A/ja
Publication of JPS625399B2 publication Critical patent/JPS625399B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
JP4177779A 1979-04-06 1979-04-06 Memory switch circuit Granted JPS55134595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4177779A JPS55134595A (en) 1979-04-06 1979-04-06 Memory switch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4177779A JPS55134595A (en) 1979-04-06 1979-04-06 Memory switch circuit

Publications (2)

Publication Number Publication Date
JPS55134595A true JPS55134595A (en) 1980-10-20
JPS625399B2 JPS625399B2 (enrdf_load_stackoverflow) 1987-02-04

Family

ID=12617793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4177779A Granted JPS55134595A (en) 1979-04-06 1979-04-06 Memory switch circuit

Country Status (1)

Country Link
JP (1) JPS55134595A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251898A (ja) * 1985-08-30 1987-03-06 Nippon Telegr & Teleph Corp <Ntt> 時分割通話路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5219008A (en) * 1975-08-05 1977-01-14 Nippon Telegr & Teleph Corp <Ntt> Memory switch system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5219008A (en) * 1975-08-05 1977-01-14 Nippon Telegr & Teleph Corp <Ntt> Memory switch system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251898A (ja) * 1985-08-30 1987-03-06 Nippon Telegr & Teleph Corp <Ntt> 時分割通話路

Also Published As

Publication number Publication date
JPS625399B2 (enrdf_load_stackoverflow) 1987-02-04

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