GB1412046A - Series-parallel shift register memory - Google Patents

Abstract

1412046 Shift register TAKACHIHO KOEKI KK 26 Sept 1973 44997/73 Heading G4C A digital memory device comprises a plurality of shift registers 1-256 (Fig. 1, Fig. 2, not shown) operable to recirculate individually or in one (Fig. 1) or two (Fig. 2) loops under the control of switches 257-512 and as an open or closed loop under the control of switch(es) 513, (513A, 513B), input data at terminal T 1 being read in by switching to the open loop mode when the input address data in a register 515 coincides with the count in counter 514 and read out, with the registers recirculating individually from a register selected by output address data in register 517 controlling a matrix 518. As described in the embodiment of Fig. 1 the 256 shift registers which are connectible in a single loop each have a capacity of 516 bits and are clocked by pulses at terminal T 2 . A counter 519, also clocked by these pulses, having a capacity of 516 supplies its carry pulses to the counter 514. A signal at terminal T 4 controls a bi-stable circuit 520 for read in or read out. In the embodiment of Fig. 2 (not shown) the read in time is halved by connecting the registers in two smaller loops, the highest bit of address data enabling one of two AND gates (527, 528) to read in data via one of two switches (513A, 513B) into a loop in which the address shift register is connected. The shift registers may be of MOS type or magneto strictive delay lines.