JPS55128838A - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device

Info

Publication number
JPS55128838A
JPS55128838A JP3554879A JP3554879A JPS55128838A JP S55128838 A JPS55128838 A JP S55128838A JP 3554879 A JP3554879 A JP 3554879A JP 3554879 A JP3554879 A JP 3554879A JP S55128838 A JPS55128838 A JP S55128838A
Authority
JP
Japan
Prior art keywords
lead wire
pellets
pellet
secured
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3554879A
Other languages
Japanese (ja)
Inventor
Tadashi Sakagami
Masami Fujii
Akira Nishi
Masahiro Naito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3554879A priority Critical patent/JPS55128838A/en
Publication of JPS55128838A publication Critical patent/JPS55128838A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To eliminate application of stress to a semiconductor pellets by soldering a lead wire to a plurality of semiconductor pellets by inserting the pellets into a recess formed on a jig while supporting the pellets by a lower lead wire when soldering the pellets secured through lower lead wire onto the same substrate to an upper lead wire.
CONSTITUTION: A lower lead wire 33 common to respective semiconductor pellets 31 is secured to the surface side of a ceramic substrate 36 mounted with a heat disdipating plate 35 through a solder layer 42 on the back surface thereof using a solder layer 43. The lead wire 33 has a projected portion for partitioning the respective pellets 31, a pellet 31 is secured through a solder layer 34 to the lower lead wire 33 of the projected portion, and when an upper lead wire 32 is mounted to the opposite side of the pellet 31, a carbon jig 51 of the following construction is employed. That is, a recess made of projections A and B is formed on the jig 51, the pellet is inserted into the recess while supporting the wire 33 with the projections A and B, the wire 32 is soldered thereto. Thus, the heights of the surfaces of the wires 32 are aligned in parallel.
COPYRIGHT: (C)1980,JPO&Japio
JP3554879A 1979-03-28 1979-03-28 Method of fabricating semiconductor device Pending JPS55128838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3554879A JPS55128838A (en) 1979-03-28 1979-03-28 Method of fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3554879A JPS55128838A (en) 1979-03-28 1979-03-28 Method of fabricating semiconductor device

Publications (1)

Publication Number Publication Date
JPS55128838A true JPS55128838A (en) 1980-10-06

Family

ID=12444770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3554879A Pending JPS55128838A (en) 1979-03-28 1979-03-28 Method of fabricating semiconductor device

Country Status (1)

Country Link
JP (1) JPS55128838A (en)

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