JPS55124360A - Setting circuit for picture signal slice level - Google Patents

Abstract

PURPOSE:To secure the automatic setting for the optimum slice level by deciding the slice level of the next scanning line according to the quantity corresponding to the envelope level at the area opposing to the white ground level of the picture signals equivalent to one scanning line. CONSTITUTION:The charging is given via picture signal VD to capacitor C1 one end of which is connected to the output end of reference voltage source 10 which generates reference level VE. The value of resistance R1 and R2 plus the capacity of capacitor C1 are set a slightly lower than the envelope of the white ground of the original to secure the follow-up substantially. Timing circuit 12 generates sample pulse VC with every end of the scanning. Sample holding circuit 11 gives the sample holding to terminal voltage VI of capacitor C1 with every pulse VC, and this sample-held voltage VS is held until next 1-line scanning is over. Comparator 13 gives the binary coding to signal VD with level VS used as the slice level. This sample- held voltage VI is that which corresponds to the envelope of the white ground level of the preceding scanning period.