JPS55153475A - Binary signal generating circuit - Google Patents

Binary signal generating circuit

Info

Publication number
JPS55153475A
JPS55153475A JP6175579A JP6175579A JPS55153475A JP S55153475 A JPS55153475 A JP S55153475A JP 6175579 A JP6175579 A JP 6175579A JP 6175579 A JP6175579 A JP 6175579A JP S55153475 A JPS55153475 A JP S55153475A
Authority
JP
Japan
Prior art keywords
voltage
signal
circuit
binary signal
peak
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6175579A
Other languages
Japanese (ja)
Inventor
Yojiro Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP6175579A priority Critical patent/JPS55153475A/en
Publication of JPS55153475A publication Critical patent/JPS55153475A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40Picture signal circuits
    • H04N1/403Discrimination between the two tones in the picture signal of a two-tone original

Abstract

PURPOSE:To enable to obtain an excellent binary signal even with an original without white part at the initial of scanning, by the sample hold of peak value immediately before a peak hold circuit which produces a threshold voltage to binarize a video signal is reset. CONSTITUTION:A video signal Sa read out and amplified A at an image sensor IS is held for the peak voltage at a peak hold circuit PH, and a voltage Pp is output to a sample hold circuit SH. The circuit PH is reset with a signal Pr from a timing pulse generator TPG within nonvideo signal period, but TPG feeds a signal Ps to the circuit SH immediately before the reset and the peak value held at the circuit PH is sample-held to output a voltage Ph. The threshold voltage dividing this voltage Ph by a resistor VR is given as the reference voltage Vs of a comparator COMP. COMP compares the signal Sa with the voltage Vs to output a binary signal. Thus, a suitable binary signal is obtained even to an original without white part at the beginning of scanning of the original.
JP6175579A 1979-05-19 1979-05-19 Binary signal generating circuit Pending JPS55153475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6175579A JPS55153475A (en) 1979-05-19 1979-05-19 Binary signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6175579A JPS55153475A (en) 1979-05-19 1979-05-19 Binary signal generating circuit

Publications (1)

Publication Number Publication Date
JPS55153475A true JPS55153475A (en) 1980-11-29

Family

ID=13180282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6175579A Pending JPS55153475A (en) 1979-05-19 1979-05-19 Binary signal generating circuit

Country Status (1)

Country Link
JP (1) JPS55153475A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60158369U (en) * 1984-03-29 1985-10-22 株式会社島津製作所 Image binarization device
JPS6477272A (en) * 1987-09-18 1989-03-23 Alps Electric Co Ltd Binarizing processing circuit
JPH03127552A (en) * 1989-10-13 1991-05-30 Fuji Photo Film Co Ltd Binarizing circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60158369U (en) * 1984-03-29 1985-10-22 株式会社島津製作所 Image binarization device
JPS6477272A (en) * 1987-09-18 1989-03-23 Alps Electric Co Ltd Binarizing processing circuit
JPH03127552A (en) * 1989-10-13 1991-05-30 Fuji Photo Film Co Ltd Binarizing circuit

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