JPS55153473A - Generating circuit for binary signal - Google Patents
Generating circuit for binary signalInfo
- Publication number
- JPS55153473A JPS55153473A JP6126879A JP6126879A JPS55153473A JP S55153473 A JPS55153473 A JP S55153473A JP 6126879 A JP6126879 A JP 6126879A JP 6126879 A JP6126879 A JP 6126879A JP S55153473 A JPS55153473 A JP S55153473A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- readout
- amount
- pulse
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/40—Picture signal circuits
- H04N1/403—Discrimination between the two tones in the picture signal of a two-tone original
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Facsimile Scanning Arrangements (AREA)
- Facsimile Image Signal Circuits (AREA)
Abstract
PURPOSE:To prevent the deterioration of video quality, by resetting the peak hold circuit holding the peak value of video signal read out, within nonvideo signal period during each readout period. CONSTITUTION:Every time the original and image sensor IS relatively move toward subscanning direction by a given amount, the control pulse to start readout is produced at the timing pulse generator TPG based on the amount of movement detecting pulse Pd from the amount of movement detecting circuit DS. The drive circuit DC supplies the drive pulse to IS so that IS can start the readout of the video signal Sa at a new scanning line unit position. Further, IS generates the reset signal Pr from TPG during the nonvideo signal period Tb on and after the end of readout of video signal at the scanning line position and resets the peak hold circuit PH. Accordingly, the threshold voltage Vs based on the peak value held at PH is reset every end of the main scanning, and the voltage Vs is produced every new main scanning and is given to the comparator COMP for the comparison with the signal Sa, allowing to produce binary signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6126879A JPS55153473A (en) | 1979-05-18 | 1979-05-18 | Generating circuit for binary signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6126879A JPS55153473A (en) | 1979-05-18 | 1979-05-18 | Generating circuit for binary signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55153473A true JPS55153473A (en) | 1980-11-29 |
Family
ID=13166300
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6126879A Pending JPS55153473A (en) | 1979-05-18 | 1979-05-18 | Generating circuit for binary signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55153473A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63131261U (en) * | 1987-02-10 | 1988-08-26 | ||
JPH03127552A (en) * | 1989-10-13 | 1991-05-30 | Fuji Photo Film Co Ltd | Binarizing circuit |
-
1979
- 1979-05-18 JP JP6126879A patent/JPS55153473A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63131261U (en) * | 1987-02-10 | 1988-08-26 | ||
JPH03127552A (en) * | 1989-10-13 | 1991-05-30 | Fuji Photo Film Co Ltd | Binarizing circuit |
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