JPS551149A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS551149A JPS551149A JP7441778A JP7441778A JPS551149A JP S551149 A JPS551149 A JP S551149A JP 7441778 A JP7441778 A JP 7441778A JP 7441778 A JP7441778 A JP 7441778A JP S551149 A JPS551149 A JP S551149A
- Authority
- JP
- Japan
- Prior art keywords
- regions
- region
- type
- layer
- grow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
- Bipolar Transistors (AREA)
Abstract
PURPOSE: To provide a semiconductor device wherein separating regions and a buried region are provided, two semiconductor layers are laminated thereon and caused to grow and subjected to heat treatment to integrate separating regions, and an element is formed on the separated region, thereby to obtain a high pressure resisting element.
CONSTITUTION: Two P+ resions 12 are diffusion-formed on a P type Si substrate and an N+ type buried region 13 is provided on the substrate 11 between said two regions. Then, an N type layer 16 is caused to grow in vapor phase on the whole surface of the substrate 11, and on said N type layer 16 two P type regions 17 corresponding to the regions 12 are provided. Further, on the whole surface of said layer 16 an N type layer 18 is caused to grow in vapor phase and on said N type layer 18, where P type regions 19 are formed in correspondence to said regions 17. Thereafter, these regions are subjected to a high temperature heat treatment for a short period of time or a low-temperature heat treatment for a long period of time to cause the region 12, 17, and 19 to rise and fall respectively, thereby to integrated them, and the region 13 is swollen upward. Then, an element region 20 is formd in the layer 18 separated by integration. According to this arrangement, a depletion layer from the region 20 does not come into contact with the region 13, and the pressure resistance is improved.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7441778A JPS551149A (en) | 1978-06-19 | 1978-06-19 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7441778A JPS551149A (en) | 1978-06-19 | 1978-06-19 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS551149A true JPS551149A (en) | 1980-01-07 |
Family
ID=13546589
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7441778A Pending JPS551149A (en) | 1978-06-19 | 1978-06-19 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS551149A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4794443A (en) * | 1984-05-28 | 1988-12-27 | Canon Kabushiki Kaisha | Semiconductor device and process for producing same |
-
1978
- 1978-06-19 JP JP7441778A patent/JPS551149A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4794443A (en) * | 1984-05-28 | 1988-12-27 | Canon Kabushiki Kaisha | Semiconductor device and process for producing same |
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