JPS55109033A - Interface circuit - Google Patents

Interface circuit

Info

Publication number
JPS55109033A
JPS55109033A JP1662779A JP1662779A JPS55109033A JP S55109033 A JPS55109033 A JP S55109033A JP 1662779 A JP1662779 A JP 1662779A JP 1662779 A JP1662779 A JP 1662779A JP S55109033 A JPS55109033 A JP S55109033A
Authority
JP
Japan
Prior art keywords
transistor
via resistance
injector current
power source
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1662779A
Other languages
Japanese (ja)
Inventor
Masaharu Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1662779A priority Critical patent/JPS55109033A/en
Publication of JPS55109033A publication Critical patent/JPS55109033A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01818—Interface arrangements for integrated injection logic (I2L)

Abstract

PURPOSE:To secure the assured ON and OFF when the voltage is decreased by preventing the injector current of the IIL circuit from branching to the earth side from the input end. CONSTITUTION:The base of bipolar transistor 6 is connected to power source 1 via resistance 3, and the collector of transistor 6 is connected directly to power source 1. The emitter of transistor 6 is earthed via resistance 28 and then connected to the base of transistor 9 of IIL circuit 7 via resistance 29. When the voltage of power source 1 becomes less than the rated level, no injector current flows to the earth side via resistance 28 from injector current input part 8 of circuit 7. But the injector current is applied directly to the base of transistor 9. Accordingly, transistor 9 is never put under the semi-conduction state even with the voltage decrement, thus securing the assured ON and OFF.
JP1662779A 1979-02-14 1979-02-14 Interface circuit Pending JPS55109033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1662779A JPS55109033A (en) 1979-02-14 1979-02-14 Interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1662779A JPS55109033A (en) 1979-02-14 1979-02-14 Interface circuit

Publications (1)

Publication Number Publication Date
JPS55109033A true JPS55109033A (en) 1980-08-21

Family

ID=11921584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1662779A Pending JPS55109033A (en) 1979-02-14 1979-02-14 Interface circuit

Country Status (1)

Country Link
JP (1) JPS55109033A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4614884A (en) * 1982-04-21 1986-09-30 Tokyo Shibaura Denki Kabushiki Kaisha Input interface circuit as a buffer of a logic device to improve the signal to noise ratio of the logic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4614884A (en) * 1982-04-21 1986-09-30 Tokyo Shibaura Denki Kabushiki Kaisha Input interface circuit as a buffer of a logic device to improve the signal to noise ratio of the logic device

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