JPS55109028A - Set/reset type flip-flop circuit - Google Patents

Set/reset type flip-flop circuit

Info

Publication number
JPS55109028A
JPS55109028A JP1667079A JP1667079A JPS55109028A JP S55109028 A JPS55109028 A JP S55109028A JP 1667079 A JP1667079 A JP 1667079A JP 1667079 A JP1667079 A JP 1667079A JP S55109028 A JPS55109028 A JP S55109028A
Authority
JP
Japan
Prior art keywords
logic
circuit
reset
flop
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1667079A
Other languages
Japanese (ja)
Inventor
Takuya Iwagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1667079A priority Critical patent/JPS55109028A/en
Publication of JPS55109028A publication Critical patent/JPS55109028A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits

Abstract

PURPOSE:To secure the shorter output emerging time due to the set or reset input by forming the flip-flop through the wired OR connection of the two negative logic via two units of the double input positive logic NAND gate each. CONSTITUTION:First logic circuit 23 is formed with two double input positive logic NAND gates 24 and 25 which receive the wired OR connection of the negative logic to each other. And the second logic circuit 26 is formed with double input positive NAND gates 27 and 28. And the flip-flop is formed with these two logic circuits 23 and 26. Both forward phase reset pulse R and beackward phase set pulses # are applied to circuit 23; while backward phase reset pulse # and forward phase set pulse S are applied to circuit 26 each. As a result, the time during which output Q and # emerge after the set or reset input applied can be reduced down to 1/2 the conventional time.
JP1667079A 1979-02-14 1979-02-14 Set/reset type flip-flop circuit Pending JPS55109028A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1667079A JPS55109028A (en) 1979-02-14 1979-02-14 Set/reset type flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1667079A JPS55109028A (en) 1979-02-14 1979-02-14 Set/reset type flip-flop circuit

Publications (1)

Publication Number Publication Date
JPS55109028A true JPS55109028A (en) 1980-08-21

Family

ID=11922745

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1667079A Pending JPS55109028A (en) 1979-02-14 1979-02-14 Set/reset type flip-flop circuit

Country Status (1)

Country Link
JP (1) JPS55109028A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4484088A (en) * 1983-02-04 1984-11-20 General Electric Company CMOS Four-transistor reset/set latch

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4484088A (en) * 1983-02-04 1984-11-20 General Electric Company CMOS Four-transistor reset/set latch

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