GB1185938A - Improvements in or relating to Electric Bistable Trigger Circuits - Google Patents

Improvements in or relating to Electric Bistable Trigger Circuits

Info

Publication number
GB1185938A
GB1185938A GB4825568A GB4825568A GB1185938A GB 1185938 A GB1185938 A GB 1185938A GB 4825568 A GB4825568 A GB 4825568A GB 4825568 A GB4825568 A GB 4825568A GB 1185938 A GB1185938 A GB 1185938A
Authority
GB
United Kingdom
Prior art keywords
signal
relating
timing pulse
gates
trigger circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4825568A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB1185938A publication Critical patent/GB1185938A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

1,185,938. D-V flip-flop. SIEMENS A.G. 11 Oct., 1968 [12 Oct., 1967], No. 48255/68. Heading H3T. A D-V type flip-flop has six NAND gates G1 to G6 interconnected as shown by the full lines in Fig. 2, an information signal D (0 or 1) appearing at the output Q a bi-stable formed by the gates G5, G6 reciprocally coupled, when both a signal (1) is present at the input V, and a timing pulse occurs at terminal T. Any change in the input D after the start of a timing pulse at T has no effect on the output Q. As an alternative to the timing pulse T, a " set " signal (0) may be used (e.g. for asynchronous pulses occurring at D) and is applied at S to the gates G2, G6. A corresponding " reset " signal (0) at R is applied to G1, G4 and G5.
GB4825568A 1967-10-12 1968-10-11 Improvements in or relating to Electric Bistable Trigger Circuits Expired GB1185938A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1967S0112370 DE1293842B (en) 1967-10-12 1967-10-12 Clock-controlled flip-flop made up of NAND gates

Publications (1)

Publication Number Publication Date
GB1185938A true GB1185938A (en) 1970-03-25

Family

ID=7531731

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4825568A Expired GB1185938A (en) 1967-10-12 1968-10-11 Improvements in or relating to Electric Bistable Trigger Circuits

Country Status (4)

Country Link
DE (1) DE1293842B (en)
FR (1) FR1589009A (en)
GB (1) GB1185938A (en)
NL (1) NL6814096A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3976949A (en) * 1975-01-13 1976-08-24 Motorola, Inc. Edge sensitive set-reset flip flop

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3976949A (en) * 1975-01-13 1976-08-24 Motorola, Inc. Edge sensitive set-reset flip flop

Also Published As

Publication number Publication date
DE1293842B (en) 1969-04-30
FR1589009A (en) 1970-03-16
NL6814096A (en) 1969-04-15

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees