JPS5489449A - Multiplier circuit - Google Patents

Multiplier circuit

Info

Publication number
JPS5489449A
JPS5489449A JP15651377A JP15651377A JPS5489449A JP S5489449 A JPS5489449 A JP S5489449A JP 15651377 A JP15651377 A JP 15651377A JP 15651377 A JP15651377 A JP 15651377A JP S5489449 A JPS5489449 A JP S5489449A
Authority
JP
Japan
Prior art keywords
register
multiplication
alu
selector
multiplier circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15651377A
Other languages
Japanese (ja)
Inventor
Takashi Rokutanda
Yukiro Shiraokawa
Keizo Aoyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15651377A priority Critical patent/JPS5489449A/en
Publication of JPS5489449A publication Critical patent/JPS5489449A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To obtain a multiplier circuit which can perform the multiplication to a register outside LSI, by providing an external register, a selector and a micro instruction register in a LSI multiplier circuit which incorporates a general-purpose register, an auxiliary register and an ALU. CONSTITUTION:Internal multiplication is set in register Rb103, and a multiplicand is put in register Ra104. A port 105 causes contents of registers 103 and 104 to pass through, and B port 106 causes contents of only register 103 to pass through. Data inputted to ALU 101 of selector 111 is selected, and the output of LSB of Q register 109 is inputted as a SEL signal. Then, A or B is selected by the SEL signal, and data is outputted. Shifter 102 shifts the output of ALU to the right. Data of a main memory, etc., is put in external register 110, and the multiplication between in ternal register as well as the multiplication between the internal register and the external registers can be performed by micro instruction register 112 and the SEL signal of selector 111.
JP15651377A 1977-12-27 1977-12-27 Multiplier circuit Pending JPS5489449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15651377A JPS5489449A (en) 1977-12-27 1977-12-27 Multiplier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15651377A JPS5489449A (en) 1977-12-27 1977-12-27 Multiplier circuit

Publications (1)

Publication Number Publication Date
JPS5489449A true JPS5489449A (en) 1979-07-16

Family

ID=15629408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15651377A Pending JPS5489449A (en) 1977-12-27 1977-12-27 Multiplier circuit

Country Status (1)

Country Link
JP (1) JPS5489449A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208644A (en) * 1983-05-12 1984-11-27 Nec Corp Data processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4958721A (en) * 1972-06-20 1974-06-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4958721A (en) * 1972-06-20 1974-06-07

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208644A (en) * 1983-05-12 1984-11-27 Nec Corp Data processor
JPH0381176B2 (en) * 1983-05-12 1991-12-27 Nippon Electric Co

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