JPS5489448A - Divider circuit - Google Patents

Abstract

PURPOSE:To perform a high-speed division by adding a flag, a selector and a micro instruction register to a LSI divider circuit which incorporates a general-purpose register, an auxiliary register and an ALU and using two clocks. CONSTITUTION:Upper Rb 8 bits and lower Q 8 bits of a dividend are put in registers 103 and 109 respectively, and the complement of divider Ra is put in register 104. The output of micro instruction register 112 is set by selector 111 and selects data inputted to ALU 101. When carrier is generated from ALU, this carrier is set in flag 113 which synchronizes with clock 2. The output of flag 113 controls the selector to execute ''Rb - Ra'' in ALU, and shifts Rb and Q registers by one bit through shifter 102 by output F, and then, this operation is repeated to put quotient in the Q register. As a result, since subtraction and shift steps are performed before the cycle completion of fundamental clock 1, a high-speed division is performed.