JPH0381176B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to a one-chip microcomputer with multiplication functionality.

Microcomputers are used for arithmetic control in audio processing, graphics processing, general data processing, etc., and among them, microcomputers are used as circuits to multiply the multiplicand by the multiplier expressed in digital binary numbers. A parallel multiplication circuit is integrated that generates partial products of multiplicands according to groups, weights these partial products according to the bits of the multiplier, and accumulates them to derive a product. However, conventionally, this multiplication circuit has been physically separated from the arithmetic logic unit (ALU) that is generally built into a microcomputer. However, since the full adder of the parallel multiplication device is dedicated to multiplication, it requires a large amount of hardware, which is a significant disadvantage in terms of increasing the degree of integration in integrated circuits such as LSI.

The present invention regards multiplication as one of the four arithmetic operations,
The hardware circuit within the chip is simplified by having the ALU of the microcomputer execute the unit that executes addition among the multiplications.

The basic structure of the present invention is to generate a partial product of the multiplicand according to a digit or a group of digits of the multiplier in parallel multiplication of a digital binary number multiplier and a multiplicand,
Weight these partial products according to the bits of the multiplier,
It is characterized by leading this to the ALU where it is accumulated and calculated, and a data line is provided to lead the data that needs to be added during multiplication to the ALU.
The multiplication result is obtained in the ALU.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a hardware block diagram of the conventional 4-bit parallel multiplier described above. As shown in FIG. 2, the unit circuit A of the multiplier consists of a circuit 1 that takes partial products, and a full adder 2 that takes the sum of the partial products, the preceding full adder, and the carry. Multiplicand X (for example, 4 bits X ₀ to X ₃ ) and multiplier Y (for example, 4 bits
To execute the multiplication X×Y of bits Y ₀ to _{Y 3} ),
As shown in FIG. 1, at least 12 unit circuits A are required, and in conventional data processing devices, this multiplier existed independently of the ALU (not shown).

FIG. 3 is a circuit diagram of a 4-bit parallel multiplier constructed as an embodiment of the present invention for comparison with the conventional one. The unit circuit is the same as that in FIG. 1, and consists of a circuit 1 for taking partial products and a full adder 2.
However, the cumulative addition is connected to ALU through data line 3 so that it is performed in ALU 4. The final product 5 is retrieved from ALU4.
Note that an AND gate is used to connect the ALU and the multiplication circuit. As in Figure 1, the multiplicand X (4
In this embodiment, only six unit circuits A are required to execute the multiplication X.times.Y of the multiplier Y (4 bits) and the multiplier Y (4 bits). The remaining additions are done through data line 3 and 6.
It can be executed by the bit ALU4 (which is originally found in microcomputer chips),
The final product Z5 is obtained as the output of this ALU.

As explained above, when performing parallel multiplication of a multiplier and a multiplicand of digital binary numbers, the present invention generates partial products of the multiplicand according to the digits or groups of digits of the multiplier, and divides these partial products according to the bits of the multiplier. A data processing device is obtained in which a component of a parallel multiplication circuit that derives a product by weighting and accumulating is replaced with an arithmetic logic unit (ALU). Therefore, there is an effect that the hardware configuration of the data processing device can be reduced and the degree of integration can be increased without impairing calculation efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional 4-bit parallel multiplier, and FIG. 2 is a unit circuit diagram thereof. A... Unit circuit, 1... Circuit that takes partial products, 2
...full adder, X...multiplicand, Y...multiplier. FIG. 3 is a circuit block diagram of a 4-bit parallel multiplier according to one embodiment of the present invention. A... Unit circuit, 3... Data line, 4...
ALU, 5...final product, X...multiplicand, Y...
…multiplier.

Claims (1)

[Claims] 1. A data processing device that executes multiplication of a multiplier and a multiplicand of a digital binary number using a logic operation device, wherein a logic gate circuit to which the multiplier and the multiplicand are supplied is provided independently of the logic operation device; The logical gate circuit is a group of logical gates that generate partial piles of the number of riding areas according to the contents of the number of vitits of the multiplier, and the remaining Bitsuto, which is at least the lowest bet of the generated part of the part of the part of the part of the part of the part of the part of the part of the part of the part of the part of the part of the partial piles. and a multiplication unit circuit that performs addition processing on data according to bit weights to generate intermediate data, and each bit of the intermediate data and each bit of the partial product that is not used in the addition processing. Further, means is provided for guiding the multiplication result from the logic operation device to the logic operation device according to the bit weight, and the logic operation device is also used as a final stage adder necessary for multiplication of the multiplier and the multiplicand. A data processing device characterized in that it obtains.