JPS5465434A - Addres system for interleave memory - Google Patents
Addres system for interleave memoryInfo
- Publication number
- JPS5465434A JPS5465434A JP13157677A JP13157677A JPS5465434A JP S5465434 A JPS5465434 A JP S5465434A JP 13157677 A JP13157677 A JP 13157677A JP 13157677 A JP13157677 A JP 13157677A JP S5465434 A JPS5465434 A JP S5465434A
- Authority
- JP
- Japan
- Prior art keywords
- plane
- line
- address
- memory
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To ensure an automatic allotment of the address by providing the adder, selective logic circuit and comparator circuit with every memory plane and then inserting the necessary number of the memory plane.
CONSTITUTION: Memroy plane 2 and 2' are connected to address bus 3, memory plane address line 12 and 12' and to interleave mode designation signal line 17 respectively. Then selective logic circuit 13 and 13' which select and deliver specified line 18 from address bus 3 according to the signals sent from line 17 are provided to every memory plane, along with comparator 14 and 14' which compare the output of circuit 13 with the contents of address line 12 to carry out the address designation and then deliver coincidence signal 11. Furthermore, the memory capacity of plane 2 is added to the contents of line 12 as well as to next plane 2' via line 12'. For this purpose, adder 15 and 15' are installed. Thus, an automatic allotment of the address is ensured for plane 2 abd 2'.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13157677A JPS5828675B2 (en) | 1977-11-04 | 1977-11-04 | Interleaved memory addressing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13157677A JPS5828675B2 (en) | 1977-11-04 | 1977-11-04 | Interleaved memory addressing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5465434A true JPS5465434A (en) | 1979-05-26 |
JPS5828675B2 JPS5828675B2 (en) | 1983-06-17 |
Family
ID=15061272
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13157677A Expired JPS5828675B2 (en) | 1977-11-04 | 1977-11-04 | Interleaved memory addressing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5828675B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0237682U (en) * | 1988-09-03 | 1990-03-13 |
-
1977
- 1977-11-04 JP JP13157677A patent/JPS5828675B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5828675B2 (en) | 1983-06-17 |
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