JPS5465434A - Addres system for interleave memory - Google Patents

Addres system for interleave memory

Info

Publication number
JPS5465434A
JPS5465434A JP13157677A JP13157677A JPS5465434A JP S5465434 A JPS5465434 A JP S5465434A JP 13157677 A JP13157677 A JP 13157677A JP 13157677 A JP13157677 A JP 13157677A JP S5465434 A JPS5465434 A JP S5465434A
Authority
JP
Japan
Prior art keywords
plane
line
address
memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13157677A
Other languages
Japanese (ja)
Other versions
JPS5828675B2 (en
Inventor
Tadaaki Bando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13157677A priority Critical patent/JPS5828675B2/en
Publication of JPS5465434A publication Critical patent/JPS5465434A/en
Publication of JPS5828675B2 publication Critical patent/JPS5828675B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To ensure an automatic allotment of the address by providing the adder, selective logic circuit and comparator circuit with every memory plane and then inserting the necessary number of the memory plane.
CONSTITUTION: Memroy plane 2 and 2' are connected to address bus 3, memory plane address line 12 and 12' and to interleave mode designation signal line 17 respectively. Then selective logic circuit 13 and 13' which select and deliver specified line 18 from address bus 3 according to the signals sent from line 17 are provided to every memory plane, along with comparator 14 and 14' which compare the output of circuit 13 with the contents of address line 12 to carry out the address designation and then deliver coincidence signal 11. Furthermore, the memory capacity of plane 2 is added to the contents of line 12 as well as to next plane 2' via line 12'. For this purpose, adder 15 and 15' are installed. Thus, an automatic allotment of the address is ensured for plane 2 abd 2'.
COPYRIGHT: (C)1979,JPO&Japio
JP13157677A 1977-11-04 1977-11-04 Interleaved memory addressing method Expired JPS5828675B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13157677A JPS5828675B2 (en) 1977-11-04 1977-11-04 Interleaved memory addressing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13157677A JPS5828675B2 (en) 1977-11-04 1977-11-04 Interleaved memory addressing method

Publications (2)

Publication Number Publication Date
JPS5465434A true JPS5465434A (en) 1979-05-26
JPS5828675B2 JPS5828675B2 (en) 1983-06-17

Family

ID=15061272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13157677A Expired JPS5828675B2 (en) 1977-11-04 1977-11-04 Interleaved memory addressing method

Country Status (1)

Country Link
JP (1) JPS5828675B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0237682U (en) * 1988-09-03 1990-03-13

Also Published As

Publication number Publication date
JPS5828675B2 (en) 1983-06-17

Similar Documents

Publication Publication Date Title
JPS5465434A (en) Addres system for interleave memory
JPS5476034A (en) Bus data transfer system
JPS5447443A (en) Semiconductor memory unit
JPS54146552A (en) Interruption control system
JPS5685130A (en) Rom access circuit
JPS53112625A (en) Bus occupation control system
JPS55121521A (en) Data bus control system
JPS5415620A (en) Buffer memory unit
JPS57125427A (en) Circuit for transmitting simultaneously command signal
JPS54106132A (en) Buffer memory access process system
JPS5488038A (en) Data processor
JPS5478633A (en) Machine number setting system
JPS5723132A (en) Acquisition system for priority right of interruption
JPS5664667A (en) Semiconductor integrated circuit system
JPS5567834A (en) Trace system for communication control unit
JPS54114935A (en) Bus scramble circuit
JPS5661083A (en) Tlb partition system
JPS54114936A (en) Bus scramble circuit
JPS57143652A (en) Extension system for memory unit
JPS5347240A (en) Control system for intermediate buffer
JPS578855A (en) Interruption processing system
JPS5685168A (en) Access control system for main storage
JPS551675A (en) Memory protect control system
JPS54110743A (en) Electronic apparatus
JPS549542A (en) Data processing system