JPS5462741A - Control system for data buffer region - Google Patents

Control system for data buffer region

Info

Publication number
JPS5462741A
JPS5462741A JP12949277A JP12949277A JPS5462741A JP S5462741 A JPS5462741 A JP S5462741A JP 12949277 A JP12949277 A JP 12949277A JP 12949277 A JP12949277 A JP 12949277A JP S5462741 A JPS5462741 A JP S5462741A
Authority
JP
Japan
Prior art keywords
unit
data
sdm
data buffer
buffer region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12949277A
Other languages
Japanese (ja)
Other versions
JPS5738929B2 (en
Inventor
Tomohito Shibata
Shigeru Hashimoto
Tadaaki Imai
Noboru Yamamoto
Kazuo Shimomichi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12949277A priority Critical patent/JPS5462741A/en
Publication of JPS5462741A publication Critical patent/JPS5462741A/en
Publication of JPS5738929B2 publication Critical patent/JPS5738929B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to select a rational region as a data buffer region by storing information on a series number simultaneously with the erasure of data, by indicating a slow-down mode state when the data buffer region is full up.
CONSTITUTION: Channel unit 4 is able to find free data buffer region 16 in main memory unit 2. However, if region 16 is full up when data is transmitted 10 from the side of sub-channel unit 5 corresponding to polling, unit 4 turns into slow-down mode SDM, and this change is indicated into STS of reception command register 19. Once the change into SDM occurs, data transmitted 10 from the side of unit 5 are erased because of no destination, but it is stored which I/O the data (information on a series number) are from judging from the contents of register 19. Then, the change into SDM causes CPU1 to process the contents of full-up regions 16 one after another and after a fixed number of regions 16 which become empty in consequence are returned to unit 4, CPU1 indicates the release of SDM to unit 4.
COPYRIGHT: (C)1979,JPO&Japio
JP12949277A 1977-10-28 1977-10-28 Control system for data buffer region Granted JPS5462741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12949277A JPS5462741A (en) 1977-10-28 1977-10-28 Control system for data buffer region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12949277A JPS5462741A (en) 1977-10-28 1977-10-28 Control system for data buffer region

Publications (2)

Publication Number Publication Date
JPS5462741A true JPS5462741A (en) 1979-05-21
JPS5738929B2 JPS5738929B2 (en) 1982-08-18

Family

ID=15010808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12949277A Granted JPS5462741A (en) 1977-10-28 1977-10-28 Control system for data buffer region

Country Status (1)

Country Link
JP (1) JPS5462741A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61240355A (en) * 1985-04-18 1986-10-25 Nec Corp I/o data processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61240355A (en) * 1985-04-18 1986-10-25 Nec Corp I/o data processing system

Also Published As

Publication number Publication date
JPS5738929B2 (en) 1982-08-18

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