JPS61240355A - I/o data processing system - Google Patents

Abstract

PURPOSE:To accomplish setting of a data buffer in the software area by separating I/O instruction from a read-instruction, and by controlling the state of vacancy of a data buffer whose output control device is set in the main storage. CONSTITUTION:Every time a new data is inputted from a peripheral equipment DEV4-1, an entry in free state is found, and its buffer address pointer is transferred to a buffer 30 of an MMU 3 and stored there. The link pointer of the entry which is pointed out until now by the first tail entry pointer, points the newly found entry, furthermore, the first fail entry pointer itself is renewed so as to point this newly found entry.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an input/output data processing method, particularly an input/output data processing method for controlling data transfer between a peripheral device and a storage device in a microprogram-controlled data processing system. It is related to the method.

[Conventional technology]

Conventionally, in order to input data generated by peripheral devices connected to a data processing system (e.g. magnetic tape device, floppy disk device, etc.) and store it in main memory, input/output commands (read commands) issued by software have been used. The input/output controller interprets the data and issues a read command to the peripheral device, which causes the peripheral device to read the data recorded on the magnetic tape medium and transfer it to main memory via the input/output controller. . In other words, during the input/output commands issued by the software, the type of command, data transfer length.

A data transfer address is set, and the input/output control device transfers data generated within the peripheral device after an input/output command is issued by software.

In addition, for peripheral devices that receive data input asynchronously, such as terminal devices connected to communication lines, the software always issues input/output commands for read commands to the input/output control device, and Control was performed to enable data input from the device. However, as communication lines become faster and input data cannot be processed before the next data input, data overruns may occur and data may be lost. Became. To solve this problem, a control method has been devised in which a plurality of data buffers are provided in the input/output control device and data input is possible regardless of the processing time of the input data by software.

[Problem that the invention seeks to solve]

However, this method requires a data buffer storage area within the input/output device, which has the disadvantage of complicating the input/output control device and increasing cost.

An object of the present invention is to eliminate the above-mentioned drawbacks and separate input/output instructions for setting multiple data transfer storage addresses from conventional data transfer control type input/output instructions (for example, read instructions). In addition, by having the input/output control device manage the free status of the data buffer set in the main memory, it is possible for no-toware to directly access the data buffer that was reserved in the input/output control device in the conventional technology. An object of the present invention is to provide an efficient data transfer control method by making it possible to set data in a software area in main memory where possible.

[Means for solving problems]

In the method of the present invention, in data transfer control between a peripheral device and a storage device in a microprogram-controlled data processing system, the data processing system inputs and processes data generated in the peripheral device via the storage device. and a data transfer address setting instruction including address information of each of a plurality of data buffers set in the storage device for transferring and storing input data; The input/output control device constituting the data processing system corresponds to each of the data buffers set in the storage device in response to the data transfer address setting command, and corresponds to an identifier indicating the occupation state of the corresponding data buffer. each entry having respective fields for storing a buffer address pointer pointing to the address of the data buffer and a link pointer holding information regarding the order in which data is stored in the corresponding data buffer; The input/output control device includes a head entry pointer for pointing to the head entry of a queue consisting of entries selected from among the entries, and a tail entry pointer for pointing to the last entry of the queue. Initializes the settings in the local memory of
When the input/output control device recognizes data input from the peripheral device, it selects one of the entries for which the identifier indicates an empty state, and selects one of the entries whose identifier indicates an empty state, and stores data in the storage device pointed to by the buffer address pointer of this entry. transfers and stores the input data in the data buffer of , updates the identifier of this entry to indicate the occupied state, and updates the tail entry pointer to point to this entry. registering this entry in the queue with a head entry pointer and any necessary updates to the link pointer;
When the read command is issued, the entry pointed to by the head entry pointer is removed from the queue by updating the head entry pointer and necessary updates to the tail entry pointer and link pointer; Update the identifier to indicate free status.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a pull diagram showing one embodiment of the present invention. This embodiment includes an arithmetic processing unit 1 (hereinafter referred to as EPUI), an input/output control unit 2 (hereinafter referred to as 10P2), a main storage device 3 (hereinafter referred to as MMU
3) and peripheral device 4-1.4-2 (hereinafter referred to as DEV4-1)
, DEV4-2).

Figure 2 shows details of l0P2.

l0P2 includes an input/output port 21, a microprogram execution control section 22, a system bus control section 23, a local memory 24, and a data transfer control section 25. Among them, the input/output boat 21 and the data transfer control section 25 are provided corresponding to the connected DEV 4-1 and DEV 4-2.

Next, as shown in FIG. 3, data is set in the local memory 24 of this l0P2, and DEV4-1. FIG. 4 is a diagram showing registers that store parameters for controlling data transfer operations to the DEV4-2.

These registers are the first head entry pointer 241-1 and the second head entry pointer 24, respectively.
1-2. First tail entry pointer 242-1. Second
It includes a tail entry pointer 242-2 and N entries 243-1 to 243-N.

Each of these entries has a busy/busy entry, as shown in Figure 4.
It has a field D that stores a 7-key identifier, a field B that stores a buffer address pointer, and a field L that stores a link pointer.

Next, FIG. 5 shows the command format of the data transfer address setting command. This instruction includes fields for an instruction code section, a data length section, and a data address section. I (with command)
The data length to be transferred and set in the local memory 24 of JP2 is specified, and the data address field is filled with I (the address of the MMU 3 in which the data to be transferred and set is stored in the local memory 24 of JP2). include.

Now, the operation of this embodiment is as follows.

The EPUI reads and executes the software instruction f in MMUB, but if the instruction is an input/output instruction C or below (I10 instruction), it issues an I10 instruction to the specified I0P2. The I10 instruction issued from the EPUI is transmitted to the system bus control unit 23 of l0P2 via the system 10000, decoded by the microprogram execution control unit 22 of l0P2, and processed by executing the corresponding microprogram. In this example, H1DEV4-1, 1) EV4-2
Prior to performing data transfer between the Issue a transfer address setting command. This instruction executes IOP 2 as described above.
The data is supplied to the microprogram execution control unit 22 of the computer, and is decoded by the microprogram 2 running there. When this instruction is decoded, the microprogram transfers the preset data of the length specified by the data length section from the address area of the main memory 3 specified by the data address section of this data transfer address setting instruction. te l0P
2 to a predetermined address area in the local memory 24 of No. 2. As a result, the various registers described above are set to initial values in the local memory 24 as follows.

That is, the first and second head entry pointers 2
41-1, 241-2, and the first and second tail entry pointers 242-1 and 242-2 are not set and are initialized to O, respectively. Next, N entries having respective fields as shown in FIG. 4 are set corresponding to each of the N independent data buffers set and secured in the buffer area 30 of the λWU3 mentioned above, and each entry has an identifier. All fields D that store ``0'' (7
field B, which stores the buffer address pointer of each entry, contains MMU3.
The value of the buffer address pointer that points to the start address of the data buffer corresponding to this entry set in the buffer area 3° of is set, and the field L that stores the link pointer of each entry is all initialized to 0. Ru.

Now, with the initial settings as above, the DE
When the microprogram execution control unit 22 of l0P2 recognizes the data input from V4-1, the input data processing microprogram in l0PZ executes each entry 2.
The contents of the identifier field D of 43-1 to 243-N (hereinafter referred to as identifier) are determined in order, and when an entry in the free state (the contents of field D is 10'') is found, this free Issues an instruction to the data transfer control unit 25 in the input/output port 21 to transfer and store the manually input data to the data buffer set in the buffer area 30 of the MMU 3 to which the buffer address pointer of the status entry points. The lever transfer is executed and the identifier of this entry is set to 11”, that is, the busy (occupied) state, and then the first head entry pointer 241-1 and the first tail entry pointer 242-1 are both set to this entry (current 243-1).

Now, in this state, when the microprogram execution control unit 22 of JP2 recognizes the data input from DEV4-1, the input data processing microprogram in 10PZ executes each input data as before. Entry 2
The identifiers 43-1 to 243-N are sequentially determined, and when an entry in the 7-ri-1 state is first found, the data buffer set in the buffer area 30 of memory 3 pointed to by the buffer address pointer of this entry is , the input data is transferred and stored as described above, and the identifier of this entry is set to ``1'', and then the first tail entry pointer 242-1 transfers the link pointer and the first Tail entry pointer 24
2-1 are both updated to point to this newly found entry.

Thus, every time new data is input from DEV4-1, an entry in the 7-lead state is found, and the input data is transferred to the data buffer of MMU3 pointed to by the buffer address pointer of the found entry. Store it, until now the first tail entry pointer 24
The link pointer of the entry pointed to in 2-1 points to this newly found entry as the next sequential entry, and the first tail entry pointer 242-1 itself points to this newly found entry. Updated to point to the entry.

Thus, as long as an entry in the seven-lead state is found, the input data will be processed without waiting for the software to process it.
Buffer area 3 of MMtl 3 corresponding to this entry
The entry is transferred and stored in the data buffer set to 0, and correspondingly this entry is stored in the data buffer set to 0.
1. It is registered as a new entry at the end (tail) of the series of queues specified by each link pointer of the intermediate entry and the first tail entry pointer 242-1.

Now, when the first head entry pointer 241-1 takes a value other than the initial setting value of 0 as described above, the microprogram issues an interrupt to the software indicating that there is data to be processed. In this process, the microprogram sets the first head entry pointer 241-
The value of the buffer 7 address pointer of the entry pointed to by 1 is reported to the buffer 7 address pointer.

The software accepts this interrupt, retrieves the transferred and stored input data from DEV4-1 from the data buffer provided in the buffer area 30 of MU3, which is pointed to by the value of the notified buffer address pointer, and stores this data. When the read process is completed, the software issues a read command to l0P2 to process data from the next DEV4-1.

Upon receiving this read command, the IUP 20 microprogram changes the identifier of the entry currently pointed to by the first head entry pointer 241-1 to ``零'' so that this entry indicates the 7-lead state, and then returns the first head entry pointer 241-1 to 1k Update this entry's link pointer to point to the other entry in the above queue (O if it does not exist), and set this entry's link pointer to O to remove this entry from the queue. Completely set to 7 li.

Thus, the updated first pet entry pointer 24
If 1-1 does not become O (that is, there are still entries registered in the queue), the microprogram again interrupts the software to indicate that there is data to process, and this interrupt As described above, the first head entry pointer 241-1 notifies the software of the buffer address pointer of the entry currently pointed to.

The software that received the interrupt in this way accepts this interrupt, retrieves the input transferred data from the data buffer in the buffer area 30 of the MMU 3 pointed to by the buffer address pointer notified by this interrupt, and processes it. Each time this process is completed, a software read command is issued, and the microprogram that receives this read command returns the current first head entry pointer 24.
The entry pointed to by 1-1 is removed from the queue as described above, and the entry point 4241 is moved to the first head entry point 4241.
-1? It is updated to point to the next entry in the samurai matrix (to the value of the link pointer of the entry from which the pick was removed). If the next entry exists in the queue (unless the updated first head entry pointer 241-1 is 0), an interrupt to the software is generated again, and this interrupt uses the value of the buffer address pointer of the new entry. Report. Also, if the next entry does not exist, the contents of the first head entry pointer 241-1 are set to O, and the above-mentioned interrupts to the software are stopped until the queue is reconfigured by the next data input. Ru.

As described above, according to this embodiment, whenever there is an input from DEV4-1, as long as there is an entry in the free state,
Regardless of software processing, the manually entered data is immediately transferred and stored in the data buffer corresponding to this free entry, and this entry is accordingly registered at the end of the queue. The queue is processed according to the first-in, first-out rule according to the processing capacity of the software. Moreover, according to this example,
The actual data buffer is set in the buffer area 30 of the MMU 3 which can be directly accessed by software and has a large capacity, and the parameters for controlling this data transfer are only set in the local memory 24 of the 10P2 as described above. It has the characteristic that it does not require a large capacity.

In addition, in the above explanation, only the case where there was data input from DEV4-1 was detailed, but
When there is data input from 4-2, the input data processing microprogram of 10P2 inputs the second input pointer to the first head entry pointer 241-1 and the first tail entry pointer 242-1, respectively. Exactly the same process as described above is performed using the head entry pointer 241-2 and the second tail entry pointer 242-2.

In this case, if the second head entry pointer 241-2 is not 0, an interrupt is issued to the software indicating that there is data to be processed, and if the first head entry pointer 241-1 is not 0, all data to be processed is issued. An interrupt to software that indicates that
Interrupts with different priority levels are used to allow software to distinguish which queue should be serviced first if interrupt requests are received from both. In addition, read commands from software include read commands for DEV4-1 and DEV4-1.
This enables the l0P2 microprogram to distinguish between the read command for EV4-2 and the first head entry pointer 241-1 and the first tail entry pointer 242 in response to the issued read command.
-1]) Processing on the queue side for data from EV4-1 Also, Fi, the second head entry pointer 241-2 and the second tail entry pointer 24
A distinction is made between processing on the queue side for data from DEV 4-2 designated by 2-2.

According to this embodiment, each entry 243-1 to 243-N
The data buffers provided in the 30-concave buffer area 30 corresponding to each of these entries may be used in any way freely and mixedly without any restrictions as long as they are in the 7-lead state. Strategies for doing this 1. It has the feature of allowing highly flexible and highly efficient use of the buff.

Note that the above is an example of the present invention, and the present invention is not limited to the above example.

For example, in the above embodiment, the peripheral device (DBV4
) is set to two, and correspondingly, two sets of head entry pointers 241 and tail entry pointers 242 are set, but it is clear that these numbers can be freely selected other than this. For example, if the number of peripheral devices is the child side, three of them are of the same type, and the other one is a high priority peripheral, data input from three of the same type For example, all these input data are
They are registered in a first queue using a head entry pointer and a first tail entry point and treated equally according to the first-in, first-out rule, and for input data from a fourth peripheral, a second head entry pointer is used. and a second tail entry pointer, and can be treated with a high priority level.

In addition, in this embodiment, only the field D for the identifier, the field B for the buffer address pointer, and the field L for the link pointer have been described as the fields of each entry. Each entry can also include a field specifying the data length.

〔Effect of the invention〕

As described above, the present invention provides data transfer control between a peripheral device and a storage device in a microprogram-controlled data processing system, in which data from a peripheral device is inputted asynchronously and gradually. By using a highly flexible means called a microprogram, without allocating a data buffer in the input/output control device that makes up the data processing system, efficient data transfer can be achieved with minimal addition of hardware. By using this method, the number of data buffers to be set can be freely set according to the processing capacity of the software in the data processing system or the transfer capacity from peripheral devices. It is possible to do this without any hardware changes, and it is also possible to share data buffers for multiple peripherals with multiple queues.
This makes it possible to provide a more flexible and highly efficient input/output data processing method.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing details of the input/output control device of this embodiment,
Figure 3 is a diagram for explaining the registers that store various parameters set in the local memory of this input/output control device, and Figure 4 is a diagram for explaining the fields included in each entry. FIG. 5 is a diagram for explaining the format of the data transfer address setting command used in this embodiment. In the figure, 1... Arithmetic processing unit (EPU), 2...
・Input/output control unit (IOP), 3...Main memory unit (MMU), 4-1, 4-2...-Peripheral equipment ff
(DEV), 21-1.21-2...I/O port, 22...Microprogram execution control unit, 23...System bus control unit, 24...・
... Local memory, 25 ... Data transfer control unit, 30 ... Buffer area, 241-1 ...
...First head entry pointer, 241-2...
...Second head entry point 'j, 242-1.
...First tail entry pointer, 242-2.
...Second tail entry pointer, 243-1~
243-N... Entry, D... Busy/7 Lee identifier field, A... Buffer address pointer field, L... Link pointer field. Rod 2 Illustrations 4 Illustrations 5 Illustrations

Claims (1)

[Claims] In data transfer control between a peripheral device and a storage device in a microprogram-controlled data processing system, the data processing system inputs and processes data generated by the peripheral device via the storage device. and a data transfer address setting instruction including address information for each of a plurality of data buffers set in the storage device for transferring and storing input data; The input/output control device constituting the data processing system corresponds to each of the data buffers set in the storage device in response to the data transfer address setting command, and corresponds to an identifier indicating the occupation state of the corresponding data buffer. each entry having respective fields for storing a buffer address pointer pointing to the address of the data buffer and a link pointer holding information regarding the order in which data is stored in the corresponding data buffer; A head entry pointer for pointing to the head entry of a queue consisting of entries selected from the queue, and a tail entry pointer for pointing to the last entry of the queue, are connected to the input/output controller's local The settings are initialized in memory, and when the input/output control device recognizes data input from the peripheral device, it selects one of the entries whose identifier indicates an empty state and uses the buffer address pointer of this entry. transfers and stores the input data in the data buffer in the storage device pointed to by the input data, updates the identifier of this entry to indicate the occupied state, and further points the tail entry pointer to this entry. register this entry in the queue by updating the head entry pointer and the link pointer as necessary; and when the read command is issued, the entry pointed to by the head entry pointer is registered in the head The entry pointer is updated and necessary updates are made to the tail entry pointer and the link pointer to remove the entry from the queue, and further update the identifier of this entry to indicate an empty state. Input/output data processing method.