JPS55134435A - Channel transfer control system - Google Patents

Channel transfer control system

Info

Publication number
JPS55134435A
JPS55134435A JP4071579A JP4071579A JPS55134435A JP S55134435 A JPS55134435 A JP S55134435A JP 4071579 A JP4071579 A JP 4071579A JP 4071579 A JP4071579 A JP 4071579A JP S55134435 A JPS55134435 A JP S55134435A
Authority
JP
Japan
Prior art keywords
channel
data
transfer
memory
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4071579A
Other languages
Japanese (ja)
Other versions
JPS5913768B2 (en
Inventor
Taiho Higuchi
Setsuo Kugimiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54040715A priority Critical patent/JPS5913768B2/en
Publication of JPS55134435A publication Critical patent/JPS55134435A/en
Publication of JPS5913768B2 publication Critical patent/JPS5913768B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE: To prevent danger of occurrence of undesired overrun from being generated, by setting arbitrarily the occupation time of a multiplexer channel dependent upon burst mode transfer according to the mode of the system.
CONSTITUTION: Multiplexer channel 2 is connected to a CPU as a host data processing unit, and further, communication control unit 1 is connected to this channel 2, and data transfer between the CPU and channel 2 is controlled according to the communication control program stored in memory 5 in unit 1. Unit 1 is provided with central control part 4 connected to memory 5, line scanning part 3 connected to the line, and channel adapter 6 which communicates data with channel 2, and transfer data is temporarily held in data buffer register 8 provided in adapter 6, and frequency of access to memory 5 is counted by access frequency counters 11 and 12. According to contents counted by counters 11 and 12, the data transfer time for communication in the burst mode is determined by burst mode transfer frequency set part 13.
COPYRIGHT: (C)1980,JPO&Japio
JP54040715A 1979-04-04 1979-04-04 Channel transfer control method Expired JPS5913768B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54040715A JPS5913768B2 (en) 1979-04-04 1979-04-04 Channel transfer control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54040715A JPS5913768B2 (en) 1979-04-04 1979-04-04 Channel transfer control method

Publications (2)

Publication Number Publication Date
JPS55134435A true JPS55134435A (en) 1980-10-20
JPS5913768B2 JPS5913768B2 (en) 1984-03-31

Family

ID=12588272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54040715A Expired JPS5913768B2 (en) 1979-04-04 1979-04-04 Channel transfer control method

Country Status (1)

Country Link
JP (1) JPS5913768B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6182261A (en) * 1984-09-11 1986-04-25 Fujitsu Ltd Transfer control system
JPS61190623A (en) * 1985-02-19 1986-08-25 Nippon Telegr & Teleph Corp <Ntt> Controller of storage device
US7107365B1 (en) * 2002-06-25 2006-09-12 Cypress Semiconductor Corp. Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6182261A (en) * 1984-09-11 1986-04-25 Fujitsu Ltd Transfer control system
JPH0353662B2 (en) * 1984-09-11 1991-08-15 Fujitsu Ltd
JPS61190623A (en) * 1985-02-19 1986-08-25 Nippon Telegr & Teleph Corp <Ntt> Controller of storage device
US7107365B1 (en) * 2002-06-25 2006-09-12 Cypress Semiconductor Corp. Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus
US7275119B2 (en) 2002-06-25 2007-09-25 Cypress Semiconductor Corp. Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus

Also Published As

Publication number Publication date
JPS5913768B2 (en) 1984-03-31

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