JPS5451485A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5451485A
JPS5451485A JP11754977A JP11754977A JPS5451485A JP S5451485 A JPS5451485 A JP S5451485A JP 11754977 A JP11754977 A JP 11754977A JP 11754977 A JP11754977 A JP 11754977A JP S5451485 A JPS5451485 A JP S5451485A
Authority
JP
Japan
Prior art keywords
substrate
type
constituting
region
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11754977A
Other languages
Japanese (ja)
Inventor
Okimitsu Yasuda
Masaaki Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11754977A priority Critical patent/JPS5451485A/en
Publication of JPS5451485A publication Critical patent/JPS5451485A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate

Abstract

PURPOSE:To make the reverse current of the PN junction to about 1/10 using Au, by selecting Pt for the impurity being life time killer and by diffusing it in the semiconductor substrate constituting MOS-IC. CONSTITUTION:The P type well region 32 is formed by diffusion at a given region of the N type Si substrate 31, the N<+> type drain region 34 the same as the N<+> source region 33 is provided, constituting the N channel MOS transistor. The P<+> type source region 35 and the P<+> type drain region 36 are formed by diffusion, constituting the P channel MOS IC, and the entire substrate 31 is covered with the oxide film 37. After that, the Pt layer 38 is evaporated at the rear side of the substrate 31 and Pt layer 38 is diffused at 800 to 1100 deg.C, and the heat treatment at about 500 deg.C for 10 minutes is made under N2 atmosphere. Thus, by diffusing Pt in the substrate 31, the MOS IC increased for the latch up resistant capability can be obtained.
JP11754977A 1977-09-30 1977-09-30 Semiconductor device Pending JPS5451485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11754977A JPS5451485A (en) 1977-09-30 1977-09-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11754977A JPS5451485A (en) 1977-09-30 1977-09-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5451485A true JPS5451485A (en) 1979-04-23

Family

ID=14714550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11754977A Pending JPS5451485A (en) 1977-09-30 1977-09-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5451485A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4408216A (en) * 1978-06-02 1983-10-04 International Rectifier Corporation Schottky device and method of manufacture using palladium and platinum intermetallic alloys and titanium barrier for low reverse leakage over wide temperature range
CN102637596A (en) * 2011-03-22 2012-08-15 南通皋鑫电子股份有限公司 Method for manufacturing high-frequency high-voltage diode by use of czochralski silicon wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4408216A (en) * 1978-06-02 1983-10-04 International Rectifier Corporation Schottky device and method of manufacture using palladium and platinum intermetallic alloys and titanium barrier for low reverse leakage over wide temperature range
CN102637596A (en) * 2011-03-22 2012-08-15 南通皋鑫电子股份有限公司 Method for manufacturing high-frequency high-voltage diode by use of czochralski silicon wafer

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