JPS5440182B2 - - Google Patents

Info

Publication number
JPS5440182B2
JPS5440182B2 JP2247374A JP2247374A JPS5440182B2 JP S5440182 B2 JPS5440182 B2 JP S5440182B2 JP 2247374 A JP2247374 A JP 2247374A JP 2247374 A JP2247374 A JP 2247374A JP S5440182 B2 JPS5440182 B2 JP S5440182B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2247374A
Other languages
Japanese (ja)
Other versions
JPS50116145A (US06582424-20030624-M00016.png
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2247374A priority Critical patent/JPS5440182B2/ja
Publication of JPS50116145A publication Critical patent/JPS50116145A/ja
Priority to US05/620,757 priority patent/US4056844A/en
Publication of JPS5440182B2 publication Critical patent/JPS5440182B2/ja
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0831Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP2247374A 1974-02-26 1974-02-26 Expired JPS5440182B2 (US06582424-20030624-M00016.png)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2247374A JPS5440182B2 (US06582424-20030624-M00016.png) 1974-02-26 1974-02-26
US05/620,757 US4056844A (en) 1974-02-26 1975-10-08 Memory control system using plural buffer address arrays

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2247374A JPS5440182B2 (US06582424-20030624-M00016.png) 1974-02-26 1974-02-26

Publications (2)

Publication Number Publication Date
JPS50116145A JPS50116145A (US06582424-20030624-M00016.png) 1975-09-11
JPS5440182B2 true JPS5440182B2 (US06582424-20030624-M00016.png) 1979-12-01

Family

ID=12083671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2247374A Expired JPS5440182B2 (US06582424-20030624-M00016.png) 1974-02-26 1974-02-26

Country Status (2)

Country Link
US (1) US4056844A (US06582424-20030624-M00016.png)
JP (1) JPS5440182B2 (US06582424-20030624-M00016.png)

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US4142234A (en) * 1977-11-28 1979-02-27 International Business Machines Corporation Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system
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US4373179A (en) * 1978-06-26 1983-02-08 Fujitsu Limited Dynamic address translation system
FR2430637A1 (fr) * 1978-07-06 1980-02-01 Cii Honeywell Bull Procede et dispositif pour garantir la coherence des informations entre des caches et d'autres memoires d'un systeme de traitement de l'information travaillant en multitraitement
US4228503A (en) * 1978-10-02 1980-10-14 Sperry Corporation Multiplexed directory for dedicated cache memory system
DE2947115A1 (de) * 1978-12-11 1980-06-26 Honeywell Inf Systems Loeschanordnung fuer einen cache- speicher eines prozessors in einem multiprozessorsystem
US4257097A (en) * 1978-12-11 1981-03-17 Bell Telephone Laboratories, Incorporated Multiprocessor system with demand assignable program paging stores
US4296475A (en) * 1978-12-19 1981-10-20 U.S. Philips Corporation Word-organized, content-addressable memory
JPS55134459A (en) * 1979-04-06 1980-10-20 Hitachi Ltd Data processing system
DE2935135C2 (de) * 1979-08-30 1983-01-20 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zum Verarbeiten von Daten in einer aus Zentralprozessor, Arbeitsspeicher und dazwischen angeordnetem Pufferspeicher bestehenden Datenverarbeitungsanlage
US4291196A (en) * 1979-11-06 1981-09-22 Frederick Electronics Corp. Circuit for handling conversation data in a distributed processing telex exchange
US4471429A (en) * 1979-12-14 1984-09-11 Honeywell Information Systems, Inc. Apparatus for cache clearing
FR2472232B1 (fr) * 1979-12-14 1988-04-22 Honeywell Inf Systems Dispositif et procede d'effacement d'antememoire
US4322795A (en) * 1980-01-24 1982-03-30 Honeywell Information Systems Inc. Cache memory utilizing selective clearing and least recently used updating
US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing
US4349871A (en) * 1980-01-28 1982-09-14 Digital Equipment Corporation Duplicate tag store for cached multiprocessor system
FR2479532B1 (fr) * 1980-04-01 1986-09-19 Bull Sa Procede et dispositif pour gerer les transferts d'informations entre un ensemble memoire et les differentes unites de traitement d'un systeme de traitement numerique de l'information
US4399506A (en) * 1980-10-06 1983-08-16 International Business Machines Corporation Store-in-cache processor means for clearing main storage
US4394731A (en) * 1980-11-10 1983-07-19 International Business Machines Corporation Cache storage line shareability control for a multiprocessor system
US4410944A (en) * 1981-03-24 1983-10-18 Burroughs Corporation Apparatus and method for maintaining cache memory integrity in a shared memory environment
US4445174A (en) * 1981-03-31 1984-04-24 International Business Machines Corporation Multiprocessing system including a shared cache
US4821184A (en) * 1981-05-22 1989-04-11 Data General Corporation Universal addressing system for a digital data processing system
US4525777A (en) * 1981-08-03 1985-06-25 Honeywell Information Systems Inc. Split-cycle cache system with SCU controlled cache clearing during cache store access period
US4420807A (en) * 1981-08-31 1983-12-13 International Business Machines Corporation Selectively holding data in a buffer for defective backing store tracks
US4504902A (en) * 1982-03-25 1985-03-12 At&T Bell Laboratories Cache arrangement for direct memory access block transfer
JPS5948879A (ja) * 1982-09-10 1984-03-21 Hitachi Ltd 記憶制御方式
JPS60500187A (ja) * 1982-12-30 1985-02-07 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン データ処理システム
JPS6093563A (ja) * 1983-10-27 1985-05-25 Hitachi Ltd バツフア記憶制御方式
JPS60138653A (ja) * 1983-12-27 1985-07-23 Hitachi Ltd 階層記憶制御方式
JPH0760422B2 (ja) * 1983-12-30 1995-06-28 株式会社日立製作所 記憶ロツク方式
US4881164A (en) * 1983-12-30 1989-11-14 International Business Machines Corporation Multi-microprocessor for controlling shared memory
DE3582506D1 (de) * 1984-02-10 1991-05-23 Prime Computer Inc Cache-kohaerenz-anordnung.
US5255369A (en) * 1984-03-10 1993-10-19 Encore Computer U.S., Inc. Multiprocessor system with reflective memory data transfer device
GB2156554B (en) * 1984-03-10 1987-07-29 Rediffusion Simulation Ltd Processing system with shared data
US5581732A (en) * 1984-03-10 1996-12-03 Encore Computer, U.S., Inc. Multiprocessor system with reflective memory data transfer device
JP2609220B2 (ja) * 1985-03-15 1997-05-14 ソニー株式会社 マルチ・プロセツサ・システム
FR2590699B1 (fr) * 1985-11-25 1994-07-01 Nec Corp Systeme assurant la coherence pour les contenus d'une antememoire
US5146607A (en) * 1986-06-30 1992-09-08 Encore Computer Corporation Method and apparatus for sharing information between a plurality of processing units
US4958273A (en) * 1987-08-26 1990-09-18 International Business Machines Corporation Multiprocessor system architecture with high availability
JPS6476345A (en) * 1987-09-18 1989-03-22 Fujitsu Ltd Disk cache control system
KR920001282B1 (ko) * 1987-10-02 1992-02-10 가부시키가이샤 히타치세이사쿠쇼 버퍼메모리 제어장치
JPH07111713B2 (ja) * 1988-02-24 1995-11-29 富士通株式会社 構成変更制御方式
DE3919802C2 (de) * 1988-06-17 1997-01-30 Hitachi Ltd Speichersteuersystem für ein Multiprozessorsystem
US5025365A (en) * 1988-11-14 1991-06-18 Unisys Corporation Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors
US5148533A (en) * 1989-01-05 1992-09-15 Bull Hn Information Systems Inc. Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache units
JPH0748191B2 (ja) * 1989-08-10 1995-05-24 株式会社日立製作所 バッファ記憶制御装置
EP0567708A1 (en) * 1992-04-30 1993-11-03 International Business Machines Corporation Apparatus for optimizing cache memory invalidation
US5717942A (en) * 1994-12-27 1998-02-10 Unisys Corporation Reset for independent partitions within a computer system
US5603005A (en) * 1994-12-27 1997-02-11 Unisys Corporation Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
US5701313A (en) * 1995-02-24 1997-12-23 Unisys Corporation Method and apparatus for removing soft errors from a memory
US5511164A (en) * 1995-03-01 1996-04-23 Unisys Corporation Method and apparatus for determining the source and nature of an error within a computer system
US6279098B1 (en) 1996-12-16 2001-08-21 Unisys Corporation Method of and apparatus for serial dynamic system partitioning
US5875201A (en) * 1996-12-30 1999-02-23 Unisys Corporation Second level cache having instruction cache parity error control
US5960455A (en) * 1996-12-30 1999-09-28 Unisys Corporation Scalable cross bar type storage controller
US5822766A (en) * 1997-01-09 1998-10-13 Unisys Corporation Main memory interface for high speed data transfer
US5970253A (en) * 1997-01-09 1999-10-19 Unisys Corporation Priority logic for selecting and stacking data
US5860093A (en) * 1997-01-21 1999-01-12 Unisys Corporation Reduced instruction processor/storage controller interface
US5940466A (en) * 1997-10-29 1999-08-17 Micron Electronics, Inc. Apparatus for counting parts in a tray
US6161153A (en) * 1998-07-30 2000-12-12 Micron Technology, Inc. Method for sharing data buffers from a buffer pool
US6282589B1 (en) 1998-07-30 2001-08-28 Micron Technology, Inc. System for sharing data buffers from a buffer pool
US7069391B1 (en) 2000-08-30 2006-06-27 Unisys Corporation Method for improved first level cache coherency
US6697925B1 (en) 2000-12-22 2004-02-24 Unisys Corporation Use of a cache ownership mechanism to synchronize multiple dayclocks
US7035908B1 (en) * 2001-07-26 2006-04-25 Lsi Logic Corporation Method for multiprocessor communication within a shared memory architecture
US6785775B1 (en) 2002-03-19 2004-08-31 Unisys Corporation Use of a cache coherency mechanism as a doorbell indicator for input/output hardware queues
KR100772379B1 (ko) * 2005-09-23 2007-11-01 삼성전자주식회사 외부 메모리 장치, 그 영상 데이터 저장 방법, 이를 이용한영상 처리 장치

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US3339183A (en) * 1964-11-16 1967-08-29 Burroughs Corp Copy memory for a digital processor
US3618040A (en) * 1968-09-18 1971-11-02 Hitachi Ltd Memory control apparatus in multiprocessor system
US3581291A (en) * 1968-10-31 1971-05-25 Hitachi Ltd Memory control system in multiprocessing system
US3771137A (en) * 1971-09-10 1973-11-06 Ibm Memory control in a multipurpose system utilizing a broadcast

Also Published As

Publication number Publication date
JPS50116145A (US06582424-20030624-M00016.png) 1975-09-11
US4056844A (en) 1977-11-01

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