DE3582506D1 - Cache-kohaerenz-anordnung. - Google Patents

Cache-kohaerenz-anordnung.

Info

Publication number
DE3582506D1
DE3582506D1 DE8585300859T DE3582506T DE3582506D1 DE 3582506 D1 DE3582506 D1 DE 3582506D1 DE 8585300859 T DE8585300859 T DE 8585300859T DE 3582506 T DE3582506 T DE 3582506T DE 3582506 D1 DE3582506 D1 DE 3582506D1
Authority
DE
Germany
Prior art keywords
cache
memory
storage locations
data processors
cit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585300859T
Other languages
English (en)
Inventor
Paul K Rodman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Prime Computer Inc
Original Assignee
Prime Computer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Prime Computer Inc filed Critical Prime Computer Inc
Application granted granted Critical
Publication of DE3582506D1 publication Critical patent/DE3582506D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
DE8585300859T 1984-02-10 1985-02-08 Cache-kohaerenz-anordnung. Expired - Fee Related DE3582506D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US57908784A 1984-02-10 1984-02-10

Publications (1)

Publication Number Publication Date
DE3582506D1 true DE3582506D1 (de) 1991-05-23

Family

ID=24315509

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585300859T Expired - Fee Related DE3582506D1 (de) 1984-02-10 1985-02-08 Cache-kohaerenz-anordnung.

Country Status (5)

Country Link
EP (1) EP0153109B1 (de)
JP (1) JPS60237553A (de)
AT (1) ATE62764T1 (de)
CA (1) CA1226959A (de)
DE (1) DE3582506D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4825360A (en) * 1986-07-30 1989-04-25 Symbolics, Inc. System and method for parallel processing with mostly functional languages
US5045996A (en) * 1986-11-12 1991-09-03 Xerox Corporation Multiprocessor cache memory housekeeping
GB2216308A (en) * 1988-03-01 1989-10-04 Ardent Computer Corp Maintaining cache consistency
DE68928454T2 (de) * 1988-07-04 1998-04-23 Sun Microsystems Inc Multiprozessorsystem mit hierarchischer cachespeicheranordnung
EP0366323A3 (de) * 1988-10-28 1991-09-18 Apollo Computer Inc. Warteschlange zur Duplikatetikettenspeicherinvalidation
US5197146A (en) * 1989-06-21 1993-03-23 Hewlett-Packard Company Method for maintaining cache coherence in a multiprocessor computer system
US5724549A (en) * 1992-04-06 1998-03-03 Cyrix Corporation Cache coherency without bus master arbitration signals

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5440182B2 (de) * 1974-02-26 1979-12-01
US4142234A (en) * 1977-11-28 1979-02-27 International Business Machines Corporation Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system
US4322795A (en) * 1980-01-24 1982-03-30 Honeywell Information Systems Inc. Cache memory utilizing selective clearing and least recently used updating
US4410944A (en) * 1981-03-24 1983-10-18 Burroughs Corporation Apparatus and method for maintaining cache memory integrity in a shared memory environment

Also Published As

Publication number Publication date
EP0153109A3 (en) 1987-09-30
EP0153109B1 (de) 1991-04-17
JPS60237553A (ja) 1985-11-26
ATE62764T1 (de) 1991-05-15
CA1226959A (en) 1987-09-15
EP0153109A2 (de) 1985-08-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee