JPS54150076A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS54150076A JPS54150076A JP5942778A JP5942778A JPS54150076A JP S54150076 A JPS54150076 A JP S54150076A JP 5942778 A JP5942778 A JP 5942778A JP 5942778 A JP5942778 A JP 5942778A JP S54150076 A JPS54150076 A JP S54150076A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- alloy
- gold
- chip
- basement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
- Die Bonding (AREA)
Abstract
PURPOSE: To increase the adhesive force by laminating the gold-zinc alloy, the gold-tin alloy and the tin in that order to the P layer side of the III-V group semiconductor chip and then carrying out the heat bonding based on the P layer.
CONSTITUTION: The Si-added layer is epitaxial-grown to GaAs to form p-layer 1 and n-layer 2. And Au-Zn alloy 4 and Au-Ge alloy 5 are formed at the layer 1 and layer 2 each. Then Au-Sn eutectic alloy 6 (80wt% of Au, 20wt% of Sn) and Sn 7 are laminated on layer 4. Chip 10 is formed by scribing and then put on basement 11 at the side of the p-layer to be heat-bonded. With this method, it is not required to insert another foil between the chip and the basement or to add vibrations. Thus, the backward characteristics is enhanced, and the using amount of gold is reduced with increased adhesive force.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5942778A JPS54150076A (en) | 1978-05-17 | 1978-05-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5942778A JPS54150076A (en) | 1978-05-17 | 1978-05-17 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54150076A true JPS54150076A (en) | 1979-11-24 |
JPS5755290B2 JPS5755290B2 (en) | 1982-11-24 |
Family
ID=13112943
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5942778A Granted JPS54150076A (en) | 1978-05-17 | 1978-05-17 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54150076A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7851910B2 (en) | 2003-04-01 | 2010-12-14 | Infineon Technologies Ag | Diffusion soldered semiconductor device |
-
1978
- 1978-05-17 JP JP5942778A patent/JPS54150076A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7851910B2 (en) | 2003-04-01 | 2010-12-14 | Infineon Technologies Ag | Diffusion soldered semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS5755290B2 (en) | 1982-11-24 |
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