JPS61181176A - Optical semiconductor device - Google Patents

Optical semiconductor device

Info

Publication number
JPS61181176A
JPS61181176A JP60021075A JP2107585A JPS61181176A JP S61181176 A JPS61181176 A JP S61181176A JP 60021075 A JP60021075 A JP 60021075A JP 2107585 A JP2107585 A JP 2107585A JP S61181176 A JPS61181176 A JP S61181176A
Authority
JP
Japan
Prior art keywords
layer
junction
silicon substrate
chip
silver paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60021075A
Other languages
Japanese (ja)
Inventor
Yuji Kawamoto
川本 裕治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60021075A priority Critical patent/JPS61181176A/en
Publication of JPS61181176A publication Critical patent/JPS61181176A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

PURPOSE:To prevent the short circuit of a junction due to the creeping-up of conductive paste while obtaining sufficient die bonding strength by bonding an silicon substrate with the base of a semiconductor chip, from a side surface of which the junction is exposed, through a silver paste layer and die-conding the silicon substrate side onto a stem substrate through conductive adhesives. CONSTITUTION:A GaAlAs infrared LED has a P-type GaAlAs layer 1, an N-type GaAlAs layer 2 and an aluminum electrode 3, and an silicon substrate 12 is bonded onto the back of the P-type GaAlAs layer 1 through a silver paste layer 11. on die bonding, conductive paste 4 is applied onto a mount section in a stem substrate 5 as a mounting agent, and a LEF pellet is fixed. Conductive adhesives 4 also creep up along the side wall of the LED chip at the time. A distance up to a junction surface from the base of the chip is made longer than a conventional GaAlAs infrared LED pellet by several hundred 4mum, thus preventing the situation, in which a P-N junction is short-circuited by creeping-up conductive paste 4, approximately completely.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は光半導体装置に関し、特に、GaAlAs赤外
発光素子に適したダイボンディング形態の改良に係る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an optical semiconductor device, and particularly to an improvement in a die bonding configuration suitable for a GaAlAs infrared light emitting device.

〔発明の技術的背景〕[Technical background of the invention]

発光ダイオード(LED)等の光半導体装置をパッケー
ジングする際には、メモリー等の他の半導体装置の場合
と同じく、LEDベレットをステム基板にダイボンディ
ングする工程が含まれる。
When packaging an optical semiconductor device such as a light emitting diode (LED), as in the case of other semiconductor devices such as a memory, a step of die bonding the LED pellet to a stem substrate is included.

従来、このダイボンディングは第2図(A)〜(D)に
示すようにして行なわれている。
Conventionally, this die bonding has been performed as shown in FIGS. 2(A) to 2(D).

第1図(A)はGaA I Asによる従来の赤外LE
Dチップを示す断面図である。同図において、1はP型
GaA I As層である。該P型層1の上にはN型G
aA I As層2が形成され、両層により発光領域と
なるPN接合が形成されている。また、N型層2の表面
にはアルミニウム躾による電極3が形成されている。こ
のGaA I As赤外LEDペレットにおけるPN接
合構造は、図示しないGaASI板上に前記のP型層1
およびN型層2を順次エピタキシャル成長させ、その後
GaAs1板を除去することにより形成されている。従
って、チップ底面から接合面までの距離d1は、通常の
半導体装置における接合面までの距離d2よりも短くな
っている。なお、このようにGaAs基板を除去する理
由は、GaAs基板による光吸収を回避して発光出力を
向上するためである。
Figure 1 (A) shows a conventional infrared LE using GaAI As.
It is a sectional view showing a D chip. In the figure, 1 is a P-type GaA I As layer. On the P-type layer 1 is an N-type G layer.
An aA I As layer 2 is formed, and both layers form a PN junction that becomes a light emitting region. Furthermore, an electrode 3 made of aluminum is formed on the surface of the N-type layer 2. The PN junction structure in this GaAI As infrared LED pellet consists of the above-mentioned P-type layer 1 on a GaASI plate (not shown).
and an N-type layer 2 are sequentially epitaxially grown, and then the GaAs 1 plate is removed. Therefore, the distance d1 from the bottom of the chip to the bonding surface is shorter than the distance d2 from the bonding surface in a normal semiconductor device. Note that the reason for removing the GaAs substrate in this manner is to avoid light absorption by the GaAs substrate and improve light emission output.

上記のLEDペレットを第2図(8)のステム基板上に
ダイボンディングするに当っては、まず導電性接着剤4
をステム基板5上のマウント部位に滴下し、同図(C)
に示すようにその上に前記LEDベレットを接着する。
When die-bonding the above LED pellets onto the stem substrate shown in FIG. 2 (8), first apply the conductive adhesive 4
was dropped on the mounting site on the stem substrate 5, and the same figure (C)
The LED pellet is glued thereon as shown in FIG.

その際、導電性接着剤4はその表面張力によりLEDチ
ップの側面に沿って這い上りを生じ、同図(D)に示す
ような形状でLEDチップを固定するようになる。
At this time, the conductive adhesive 4 creeps up along the side surface of the LED chip due to its surface tension, and the LED chip is fixed in the shape shown in FIG.

ところで、導電性接着剤4の這い上りがLEDチップの
PN接合面にまで達すると、P型層1とN型層2とが短
絡してLEDとして機能しなくなってしまう。接合面ま
での距離d!が小さいQaAIAS赤外LEDではその
危険性が大であるため、この場合には導電性接着剤4と
して這い上りの小さいポリイミド系の銀ペーストを用い
、且つその使用量を少なくすることにより、マウント剤
の這い上りによる短絡を防止している。
By the way, if the conductive adhesive 4 creeps up to the PN junction surface of the LED chip, the P-type layer 1 and the N-type layer 2 will be short-circuited and the LED will no longer function. Distance d to the joint surface! The risk of this is great for QaAIAS infrared LEDs, which have a small amount of water, so in this case, a polyimide-based silver paste with a small creep-up is used as the conductive adhesive 4, and by reducing the amount used, the mounting agent This prevents short circuits caused by creeping up.

〔背景技術の問題点〕 ところが、ポリイミド系銀ペーストは塗布後の硬化速度
が速いため、放置時間が長くなると粘度が著しく劣化し
てペレットとの馴染みが悪くなり、またマウント作業の
バラツキにより強度が保持されていないものが出てくる
問題があった。また、這い上り防止のために導電性接着
剤の使用量を既述のように少なくしているから、上記の
粘度劣化による影響ともあいまって、ペレットの剥離を
生じる易くなるという問題があった。
[Problems with the background technology] However, polyimide silver paste cures quickly after application, so if left for a long time, the viscosity deteriorates significantly, making it less compatible with the pellets, and the strength decreases due to variations in mounting work. There was a problem where some items were not retained. Further, since the amount of conductive adhesive used is reduced as described above to prevent creeping up, there is a problem in that the pellets are likely to peel off due to the influence of the above-mentioned viscosity deterioration.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、LED等の
光半導体装置をアセンブリーする際のダイボンディング
において、導電性ペーストの這い上りによる接合の短絡
を防止すると共に、充分な量の導電性接着剤を使用して
ダイボンディング強度を得ることを目的とするものであ
る。
The present invention has been made in view of the above-mentioned circumstances, and is intended to prevent short-circuiting of the bond due to the creeping up of conductive paste in die bonding when assembling optical semiconductor devices such as LEDs, and to provide a sufficient amount of conductive adhesive. The purpose is to obtain die bonding strength using a chemical agent.

〔発明の概要〕[Summary of the invention]

本発明による光半導体装置は、第一導電型GaAIAS
層および第二導電型GaAl As層からなるPN接合
を有し、且つ該接合が側面に露出している半導体チップ
と、該半導体チップの底面に銀ペースト層を介して接着
されたシリコン基板とを具備し、該シリコン基板側を導
電性接着剤を介してステム基板上にダイボンディングす
るようにしたことを特徴とするものである。
The optical semiconductor device according to the present invention is made of first conductivity type GaAIAS.
A semiconductor chip having a PN junction consisting of a second conductivity type GaAlAs layer and a second conductivity type GaAlAs layer and with the junction exposed on the side surface, and a silicon substrate bonded to the bottom surface of the semiconductor chip via a silver paste layer. The invention is characterized in that the silicon substrate side is die-bonded onto the stem substrate via a conductive adhesive.

上記本発明の光半導体装置では従来の半導体チップの裏
面にシリコン基板を接着しているため、その厚さ分く通
常は数百−)だけPN接合までの距離が長くなり、マウ
ント剤を十分に使用しても−その這い上りで接合間が短
絡する事態を防止することができる。
In the above-mentioned optical semiconductor device of the present invention, since a silicon substrate is bonded to the back side of a conventional semiconductor chip, the distance to the PN junction is longer by the thickness of the silicon substrate, which is usually several hundred - Even when used, it is possible to prevent short circuits between the joints due to creeping up.

また、GaA I As層とシリコン基板との間には銀
ペースト層が介在されているため、本発明をLEDに適
用した場合、GaA l aAsの接合で発生した光は
この銀ペースト層で反射され、シリコン基板中で吸収さ
れることなく外部に取出されるから従来と同じ発光出力
が得られる。
Furthermore, since a silver paste layer is interposed between the GaAl As layer and the silicon substrate, when the present invention is applied to an LED, the light generated by the GaAl As bonding is reflected by this silver paste layer. Since the light is taken out to the outside without being absorbed in the silicon substrate, the same light emitting output as before can be obtained.

〔発明の実施例〕[Embodiments of the invention]

第1図(A)は、本発明をGaAlAs赤外LEDに適
用した一実施例を示す断面図である。同図におイテ、1
はP型GaAIAS層、2はN型GaA I A s層
、3はアルミニウム電極であり、この部分の構成は第2
図(A>の従来のLEDベレットと全く同じである。他
方、この実施例ではP型GaA I As層1の裏面に
銀ペースト層11を介してシリコン基板12が接着され
ていおり、この構成が付加されている点で第2図(A)
の従来の赤外LEDベレットと異なっている。
FIG. 1(A) is a sectional view showing an embodiment in which the present invention is applied to a GaAlAs infrared LED. In the same figure, 1
is a P-type GaAIAS layer, 2 is an N-type GaAIAS layer, and 3 is an aluminum electrode, and the structure of this part is the second one.
It is exactly the same as the conventional LED pellet shown in Figure (A).On the other hand, in this embodiment, a silicon substrate 12 is bonded to the back surface of the P-type GaAI As layer 1 via a silver paste layer 11, and this structure Figure 2 (A) shows the added points.
This is different from conventional infrared LED pellets.

上記実施例の赤外LEDベレットをパッケージにアセン
ブリーする場合、これをダイボンディングするに際して
は、第1図(B)〜(D)に示すように従来と同様に行
なうことができる。即ち、まず同図(B)に示すように
ステム基板5のマウント部上にマウント剤として導電性
ペースト4を塗布した後、同図(C)に示すようにLE
Dペレットを固着すればよい。
When assembling the infrared LED pellet of the above embodiment into a package, die bonding can be performed in a conventional manner as shown in FIGS. 1(B) to 1(D). That is, first, as shown in the same figure (B), after applying the conductive paste 4 as a mounting agent on the mounting part of the stem substrate 5, as shown in the same figure (C), the LE
All you have to do is fix the D pellet.

この場合にも、導電性接着剤4は同図(D>に示すよう
にLEDチップ側壁に沿って這い上りを生じる。しかし
この実施例においては、従来のGaAlAs赤外LED
ベレットの場合に比べてチップ底面から接合面までの距
離が数百−だけ長くなっているから、這い上った導電性
ペースト4によってPN接合が短絡される事態を略完全
に防止できる。その結果、上記実施例では次のような効
果が得られる。
In this case as well, the conductive adhesive 4 creeps up along the side wall of the LED chip as shown in FIG.
Since the distance from the bottom of the chip to the bonding surface is several hundred meters longer than in the case of a pellet, it is possible to almost completely prevent the PN junction from being short-circuited by the conductive paste 4 that has climbed up. As a result, the following effects can be obtained in the above embodiment.

第一に、接合の短絡を機具することなく充分な量の導電
性ペースト4を使用できるため、LEDチップに充分な
ダイボンディング強度を得ることができ、その後の剥離
といった問題を回避することができる。
First, since a sufficient amount of conductive paste 4 can be used without shorting the bond, sufficient die bonding strength can be obtained for the LED chip, and problems such as subsequent peeling can be avoided. .

第二には、特に這い上りの少ないポリイミド系接着剤を
マウント剤に用いる必要がないため、他の半導体装置の
場合と同様、エポキシ系銀ペーストを使用してダイボン
ディングを行なうことができる。従って、ポリイミド系
銀ペーストを用いる場合の問題、即ち、塗布後の硬化速
度が速いため放置時間が長くなると粘度が著しく劣化し
てベレットとの馴染みが悪くなり、またマウント作業の
バラツキにより強度が保持されていないものが出てくる
といった問題を回避することができる。
Second, since there is no need to use a polyimide adhesive that exhibits little creeping up as a mounting agent, die bonding can be performed using an epoxy silver paste as in the case of other semiconductor devices. Therefore, there are problems when using polyimide-based silver paste, namely, the curing speed after application is fast, so if it is left for a long time, the viscosity deteriorates significantly and the compatibility with the pellet becomes poor, and the strength is not maintained due to variations in mounting work. It is possible to avoid problems such as items appearing that were not specified.

第三に、従来の場合には銀ペーストの這い上りによる接
合の短絡をチェックするため全数を外観検査する必要が
あったが、上記実施例ではこのような検査は不要である
。従って、作業時間を大幅に短縮し生産性を向上するこ
とができる。
Thirdly, in the conventional case, it was necessary to perform a visual inspection on all the pieces to check for short circuits in the joints due to silver paste creeping up, but in the above embodiment, such an inspection is not necessary. Therefore, working time can be significantly shortened and productivity can be improved.

なお上記の実施例において、PN接合で発生した赤外光
がシリコン基板12に入り込むと、シリコンによる光吸
収で外部に取出される発光出力が低下することになる。
Note that in the above embodiment, when infrared light generated at the PN junction enters the silicon substrate 12, the light emission output extracted to the outside is reduced due to light absorption by the silicon.

しかし、上記実施例では介在された銀ペースト層11で
介在されているため光はこの銀ペースト層11で反射さ
れてシリコン基板12中には侵入せず、従って従来と同
様の発光出力が得られる。
However, in the above embodiment, since the light is interposed by the silver paste layer 11, the light is reflected by the silver paste layer 11 and does not enter the silicon substrate 12, so that the same light emitting output as the conventional one can be obtained. .

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明による光半導体装置では、
半導体チップををアセンブリーする際のダイボンディン
グにおいて導電性ペーストの這い上りによる接合の短絡
を防止すると共に、充分な量の導電性接着剤を使用して
ダイボンディング強度を確保できる等、顕著な効果が得
られるものである。
As detailed above, in the optical semiconductor device according to the present invention,
In die bonding when assembling semiconductor chips, it has remarkable effects such as preventing short circuits due to conductive paste creeping up and ensuring die bonding strength by using a sufficient amount of conductive adhesive. That's what you get.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)は本発明をGaA I AS赤外LEDに
適用した一実施例を示す断面図であり、同図(B)〜(
D)はそのダイボンディング方法を示す説明図、第2図
(A)〜(D)は従来のGaAJAS赤外LE[)チッ
プの構造と、これをダイボンディングする際の問題点を
示す説明図である。 1−P型GaAl AS層、2−N型GaAIAS層、
3・・・アルミニウム電極、4・・・マウント剤、5・
・・ステム基板、11・・・銀ペースト層、12シリコ
ン基板。 出願人代理人 弁理士 鈴江武彦 第 1 図 第2匡
FIG. 1(A) is a sectional view showing an embodiment in which the present invention is applied to a GaAI AS infrared LED, and FIG. 1(B) to (
D) is an explanatory diagram showing the die bonding method, and Figures 2 (A) to (D) are explanatory diagrams showing the structure of a conventional GaAJAS infrared LE[) chip and problems when die bonding it. be. 1-P type GaAl AS layer, 2-N type GaAIAS layer,
3... Aluminum electrode, 4... Mounting agent, 5...
... Stem substrate, 11... Silver paste layer, 12 Silicon substrate. Applicant's agent Patent attorney Takehiko Suzue No. 1 Figure 2 Tadashi

Claims (1)

【特許請求の範囲】[Claims]  第一導電型GaAlAs層および第二導電型GaAl
As層からなるPN接合を有し、且つ該接合が側面に露
出している半導体チップと、該半導体チップの底面に銀
ペースト層を介して接着されたシリコン基板とを具備し
、該シリコン基板側を導電性接着剤を介してステム基板
上にダイボンディングするようにしたことを特徴とする
光半導体装置。
First conductivity type GaAlAs layer and second conductivity type GaAl
A semiconductor chip having a PN junction made of an As layer and with the junction exposed on the side surface, and a silicon substrate bonded to the bottom surface of the semiconductor chip via a silver paste layer, the silicon substrate side An optical semiconductor device characterized in that the above is die-bonded onto a stem substrate via a conductive adhesive.
JP60021075A 1985-02-06 1985-02-06 Optical semiconductor device Pending JPS61181176A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60021075A JPS61181176A (en) 1985-02-06 1985-02-06 Optical semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60021075A JPS61181176A (en) 1985-02-06 1985-02-06 Optical semiconductor device

Publications (1)

Publication Number Publication Date
JPS61181176A true JPS61181176A (en) 1986-08-13

Family

ID=12044768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60021075A Pending JPS61181176A (en) 1985-02-06 1985-02-06 Optical semiconductor device

Country Status (1)

Country Link
JP (1) JPS61181176A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS646054U (en) * 1987-06-30 1989-01-13
EP2053709B1 (en) * 2007-10-22 2012-08-01 TRUMPF Laser GmbH + Co. KG Mount for optical components

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS646054U (en) * 1987-06-30 1989-01-13
EP2053709B1 (en) * 2007-10-22 2012-08-01 TRUMPF Laser GmbH + Co. KG Mount for optical components

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