JPS54144177A - Manufacturing mask for semiconductor device - Google Patents

Manufacturing mask for semiconductor device

Info

Publication number
JPS54144177A
JPS54144177A JP5237578A JP5237578A JPS54144177A JP S54144177 A JPS54144177 A JP S54144177A JP 5237578 A JP5237578 A JP 5237578A JP 5237578 A JP5237578 A JP 5237578A JP S54144177 A JPS54144177 A JP S54144177A
Authority
JP
Japan
Prior art keywords
substrate
alignment
mask
mask plate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5237578A
Other languages
Japanese (ja)
Inventor
Seiji Yasuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5237578A priority Critical patent/JPS54144177A/en
Publication of JPS54144177A publication Critical patent/JPS54144177A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE: To make easy for alignment, by providing the steps toward two directions at one surface of the mask plate.
CONSTITUTION: The alignment OF3b is made with an angle θ to the orientation flat OF3a of the substrate 3. The step 4b matching with the OF3a,3b is provided with the major plane 4a of the glass mask plate 4, and the step thickness t2 is taken as t1≥2t2, where; t1 is the thickness of the substrate 3, and when the mask plate 4 is mounted on the both sides of the substrate 3, they are adhered. Further, on the glass mask, opaque pattern is drawn at the specified position. With this constitution, mask alignment can be easier and the accuracy is not different from conventional devices.
COPYRIGHT: (C)1979,JPO&Japio
JP5237578A 1978-05-02 1978-05-02 Manufacturing mask for semiconductor device Pending JPS54144177A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5237578A JPS54144177A (en) 1978-05-02 1978-05-02 Manufacturing mask for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5237578A JPS54144177A (en) 1978-05-02 1978-05-02 Manufacturing mask for semiconductor device

Publications (1)

Publication Number Publication Date
JPS54144177A true JPS54144177A (en) 1979-11-10

Family

ID=12913049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5237578A Pending JPS54144177A (en) 1978-05-02 1978-05-02 Manufacturing mask for semiconductor device

Country Status (1)

Country Link
JP (1) JPS54144177A (en)

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