JPS54142018A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS54142018A
JPS54142018A JP4931078A JP4931078A JPS54142018A JP S54142018 A JPS54142018 A JP S54142018A JP 4931078 A JP4931078 A JP 4931078A JP 4931078 A JP4931078 A JP 4931078A JP S54142018 A JPS54142018 A JP S54142018A
Authority
JP
Japan
Prior art keywords
address
register
transfer period
logic
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4931078A
Other languages
English (en)
Other versions
JPS5847742B2 (ja
Inventor
Fumitaka Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53049310A priority Critical patent/JPS5847742B2/ja
Publication of JPS54142018A publication Critical patent/JPS54142018A/ja
Publication of JPS5847742B2 publication Critical patent/JPS5847742B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP53049310A 1978-04-27 1978-04-27 記憶制御方式 Expired JPS5847742B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53049310A JPS5847742B2 (ja) 1978-04-27 1978-04-27 記憶制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53049310A JPS5847742B2 (ja) 1978-04-27 1978-04-27 記憶制御方式

Publications (2)

Publication Number Publication Date
JPS54142018A true JPS54142018A (en) 1979-11-05
JPS5847742B2 JPS5847742B2 (ja) 1983-10-24

Family

ID=12827368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53049310A Expired JPS5847742B2 (ja) 1978-04-27 1978-04-27 記憶制御方式

Country Status (1)

Country Link
JP (1) JPS5847742B2 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60114953A (ja) * 1983-10-31 1985-06-21 サン・マイクロシステムズ・インコーポレーテツド アドレス翻訳を採用するコンピユータ装置
JPS61166646A (ja) * 1985-01-19 1986-07-28 Panafacom Ltd メモリアクセス制御方式

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60114953A (ja) * 1983-10-31 1985-06-21 サン・マイクロシステムズ・インコーポレーテツド アドレス翻訳を採用するコンピユータ装置
JPH0584532B2 (ja) * 1983-10-31 1993-12-02 Sun Microsystems Inc
JPS61166646A (ja) * 1985-01-19 1986-07-28 Panafacom Ltd メモリアクセス制御方式

Also Published As

Publication number Publication date
JPS5847742B2 (ja) 1983-10-24

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