JPS54136243A - Address conversion circuit - Google Patents

Address conversion circuit

Info

Publication number
JPS54136243A
JPS54136243A JP4334278A JP4334278A JPS54136243A JP S54136243 A JPS54136243 A JP S54136243A JP 4334278 A JP4334278 A JP 4334278A JP 4334278 A JP4334278 A JP 4334278A JP S54136243 A JPS54136243 A JP S54136243A
Authority
JP
Japan
Prior art keywords
address
bit
program
mux3
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4334278A
Other languages
Japanese (ja)
Inventor
Koji Nagafune
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4334278A priority Critical patent/JPS54136243A/en
Publication of JPS54136243A publication Critical patent/JPS54136243A/en
Pending legal-status Critical Current

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  • Memory System (AREA)

Abstract

PURPOSE: To decrease the number of steps for program, by converting the same input addresses to different address with the control signal.
CONSTITUTION: The input signal is the memory address of n-bit and the control signals 1 to n. The encoder 1 produces the address pattern of m-bit with the control signal and it is inputted to the multiplexer MUX 3. Among the n-bit of input signals, the decoder 2 decodes the address fo n-l- bit, produces the signal which address of any set is used for MUX3 and is fed to MUX3. MUX3 selects whether the m-bit of the input signal is used or the m-bit of the output of the encoder 1 is used, and it is inputted to the memory address register 4. Accordingly, the control signal can convert the same input address on program to different physical address to simplify the program.
COPYRIGHT: (C)1979,JPO&Japio
JP4334278A 1978-04-14 1978-04-14 Address conversion circuit Pending JPS54136243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4334278A JPS54136243A (en) 1978-04-14 1978-04-14 Address conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4334278A JPS54136243A (en) 1978-04-14 1978-04-14 Address conversion circuit

Publications (1)

Publication Number Publication Date
JPS54136243A true JPS54136243A (en) 1979-10-23

Family

ID=12661161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4334278A Pending JPS54136243A (en) 1978-04-14 1978-04-14 Address conversion circuit

Country Status (1)

Country Link
JP (1) JPS54136243A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54157447A (en) * 1978-06-02 1979-12-12 Hitachi Ltd Automatic control unit
JPS58223831A (en) * 1982-06-23 1983-12-26 Nec Corp Selecting system of input and output device
JPS5983234A (en) * 1982-11-02 1984-05-14 Matsushita Electronics Corp Large scale integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54157447A (en) * 1978-06-02 1979-12-12 Hitachi Ltd Automatic control unit
JPS58223831A (en) * 1982-06-23 1983-12-26 Nec Corp Selecting system of input and output device
JPS5983234A (en) * 1982-11-02 1984-05-14 Matsushita Electronics Corp Large scale integrated circuit
JPH0430058B2 (en) * 1982-11-02 1992-05-20

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