JPS5512482A - Signal converting system for imtegrated circuit for watch - Google Patents

Signal converting system for imtegrated circuit for watch

Info

Publication number
JPS5512482A
JPS5512482A JP8591278A JP8591278A JPS5512482A JP S5512482 A JPS5512482 A JP S5512482A JP 8591278 A JP8591278 A JP 8591278A JP 8591278 A JP8591278 A JP 8591278A JP S5512482 A JPS5512482 A JP S5512482A
Authority
JP
Japan
Prior art keywords
signals
circuit
registers
converted
segment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8591278A
Other languages
Japanese (ja)
Inventor
Takashi Yonehara
Hideaki Aya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP8591278A priority Critical patent/JPS5512482A/en
Publication of JPS5512482A publication Critical patent/JPS5512482A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the circuit by combining and converting segment signals into logic signals as address signals so that the preset binary and decimal signals stored in advanve are read out and converted.
CONSTITUTION: Segment signals a3 to g3 of one digit of minute, signals a2 to g2 of two digits and signals a1 to g1 of one digit of hour are generated from an integrated circuit 3. Among those, AND is obtained between the signals a and b, and a and g by logic circuits 41 to 46 and fed to the A registers of CPU 5. On the other hand, the remaining signals c to f are fed to B registers. In accordance with the AND and signals e and f supplied, the A and B registers lead out address signals. In response to the address signals, the binary and decimal codes corresponding to the segment signals stored in a memory 6 are read out and converted. With the use of such simple construction, the respective segment signals can be converted into BCD codes.
COPYRIGHT: (C)1980,JPO&Japio
JP8591278A 1978-07-13 1978-07-13 Signal converting system for imtegrated circuit for watch Pending JPS5512482A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8591278A JPS5512482A (en) 1978-07-13 1978-07-13 Signal converting system for imtegrated circuit for watch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8591278A JPS5512482A (en) 1978-07-13 1978-07-13 Signal converting system for imtegrated circuit for watch

Publications (1)

Publication Number Publication Date
JPS5512482A true JPS5512482A (en) 1980-01-29

Family

ID=13872015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8591278A Pending JPS5512482A (en) 1978-07-13 1978-07-13 Signal converting system for imtegrated circuit for watch

Country Status (1)

Country Link
JP (1) JPS5512482A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57139566A (en) * 1981-02-17 1982-08-28 Gunze Kk Removal of disposed knitted part of traverse knitted fabric

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57139566A (en) * 1981-02-17 1982-08-28 Gunze Kk Removal of disposed knitted part of traverse knitted fabric
JPS6215669B2 (en) * 1981-02-17 1987-04-08 Gunze Kk

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