JPS5413264A - Bonding method of semiconductor chip - Google Patents

Bonding method of semiconductor chip

Info

Publication number
JPS5413264A
JPS5413264A JP7781877A JP7781877A JPS5413264A JP S5413264 A JPS5413264 A JP S5413264A JP 7781877 A JP7781877 A JP 7781877A JP 7781877 A JP7781877 A JP 7781877A JP S5413264 A JPS5413264 A JP S5413264A
Authority
JP
Japan
Prior art keywords
semiconductor chip
bonding method
highly accurate
tray
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7781877A
Other languages
Japanese (ja)
Inventor
Shiyouichi Ogata
Hiroshi Oishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7781877A priority Critical patent/JPS5413264A/en
Publication of JPS5413264A publication Critical patent/JPS5413264A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE: To perform highly accurate bonding with decreased number processes, by automatically perofrming highly accurate chip alignment by using a metal tray in advance and by picking up chips directly from the tray through the use of heated bonding collet.
COPYRIGHT: (C)1979,JPO&Japio
JP7781877A 1977-07-01 1977-07-01 Bonding method of semiconductor chip Pending JPS5413264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7781877A JPS5413264A (en) 1977-07-01 1977-07-01 Bonding method of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7781877A JPS5413264A (en) 1977-07-01 1977-07-01 Bonding method of semiconductor chip

Publications (1)

Publication Number Publication Date
JPS5413264A true JPS5413264A (en) 1979-01-31

Family

ID=13644601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7781877A Pending JPS5413264A (en) 1977-07-01 1977-07-01 Bonding method of semiconductor chip

Country Status (1)

Country Link
JP (1) JPS5413264A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4933299A (en) * 1972-07-26 1974-03-27

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4933299A (en) * 1972-07-26 1974-03-27

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