JPS54122982A - Manufacture for complementary mos integrated circuit device - Google Patents

Manufacture for complementary mos integrated circuit device

Info

Publication number
JPS54122982A
JPS54122982A JP1519678A JP1519678A JPS54122982A JP S54122982 A JPS54122982 A JP S54122982A JP 1519678 A JP1519678 A JP 1519678A JP 1519678 A JP1519678 A JP 1519678A JP S54122982 A JPS54122982 A JP S54122982A
Authority
JP
Japan
Prior art keywords
film
type region
channel
coated
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1519678A
Other languages
Japanese (ja)
Other versions
JPS6041870B2 (en
Inventor
Toshimoto Kodaira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP53015196A priority Critical patent/JPS6041870B2/en
Publication of JPS54122982A publication Critical patent/JPS54122982A/en
Publication of JPS6041870B2 publication Critical patent/JPS6041870B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Abstract

PURPOSE:To reduce the dead zone at the boundary of two channel regions, by injecting boron and phosphorus ions by taking the field oxide film provided at the boundary of N channel and P channel as a mask. CONSTITUTION:The SiO2 film 2 is formed along with the circuit pattern on the N type Si substrate 1, and the resist film 3 is provided at the part being P<-> type region later. Next, by taking those as masks, phosphorus ions are injected to form the N<-> type region 5, and then, the P<-> type region 6 is formed by injecting boron ions and covering the region 5 with the resist film 4. After that, the regions 5, 6 are pressed and diffused, and the films 3 and 4 are removed, and the SiO2 film 7 and the Si3B4 film 8 are coated on the entire surface. Next, the films 7, 8 of the element region are removed, and the gate SiO2 film 9 is coated on it, the gate wiring 10 is formed on it, and the P<+> type region 12 and the N<+> type region 11 are formed by ion injection at the P and N channel elements. After that, the SiO2 film 15 is coated, to provide opening and form the polycrystal Si layer 13, and the Al film 14 is evaporated on it.
JP53015196A 1978-02-13 1978-02-13 Method for manufacturing complementary MOS integrated circuit device Expired JPS6041870B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53015196A JPS6041870B2 (en) 1978-02-13 1978-02-13 Method for manufacturing complementary MOS integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53015196A JPS6041870B2 (en) 1978-02-13 1978-02-13 Method for manufacturing complementary MOS integrated circuit device

Publications (2)

Publication Number Publication Date
JPS54122982A true JPS54122982A (en) 1979-09-22
JPS6041870B2 JPS6041870B2 (en) 1985-09-19

Family

ID=11882098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53015196A Expired JPS6041870B2 (en) 1978-02-13 1978-02-13 Method for manufacturing complementary MOS integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6041870B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59210660A (en) * 1983-02-23 1984-11-29 テキサス・インスツルメンツ・インコ−ポレイテツド Method of producing cmos device
US5091332A (en) * 1990-11-19 1992-02-25 Intel Corporation Semiconductor field oxidation process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59210660A (en) * 1983-02-23 1984-11-29 テキサス・インスツルメンツ・インコ−ポレイテツド Method of producing cmos device
US5091332A (en) * 1990-11-19 1992-02-25 Intel Corporation Semiconductor field oxidation process

Also Published As

Publication number Publication date
JPS6041870B2 (en) 1985-09-19

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