JPS54122939A - Decoder circuit - Google Patents

Decoder circuit

Info

Publication number
JPS54122939A
JPS54122939A JP3077778A JP3077778A JPS54122939A JP S54122939 A JPS54122939 A JP S54122939A JP 3077778 A JP3077778 A JP 3077778A JP 3077778 A JP3077778 A JP 3077778A JP S54122939 A JPS54122939 A JP S54122939A
Authority
JP
Japan
Prior art keywords
circuit
simplicity
drain
node
mos memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3077778A
Other languages
Japanese (ja)
Inventor
Toshio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3077778A priority Critical patent/JPS54122939A/en
Publication of JPS54122939A publication Critical patent/JPS54122939A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Abstract

PURPOSE:To realize the stable operation of IC MOS memory and the simplicity of circuit, by taking the charging circuit as static type load circuit. CONSTITUTION:The logic output node A such as NOR or AND circuit etc. constituting the dynamic type decoder is fed to the gate of Qw, bootstrap transistor. Further, the source follower output produced with the active pulse phiW of drain of Qw is coupled with one drain node B of transistor pair QS1 and QS2 in cross connection, and the charging circuit QL is provided with the drain node c. In this case, the static type load circuit is adopted for the circuit QL, then the stabilization of operation of the integrated circuit MOS memory and the simplicity of circuit can be realized.
JP3077778A 1978-03-16 1978-03-16 Decoder circuit Pending JPS54122939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3077778A JPS54122939A (en) 1978-03-16 1978-03-16 Decoder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3077778A JPS54122939A (en) 1978-03-16 1978-03-16 Decoder circuit

Publications (1)

Publication Number Publication Date
JPS54122939A true JPS54122939A (en) 1979-09-22

Family

ID=12313103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3077778A Pending JPS54122939A (en) 1978-03-16 1978-03-16 Decoder circuit

Country Status (1)

Country Link
JP (1) JPS54122939A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4490628A (en) * 1980-10-29 1984-12-25 Tokyo Shibaura Denki Kabushiki Kaisha MOS Decoder selection circuit having a barrier transistor whose non-conduction period is unaffected by substrate potential disturbances

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4490628A (en) * 1980-10-29 1984-12-25 Tokyo Shibaura Denki Kabushiki Kaisha MOS Decoder selection circuit having a barrier transistor whose non-conduction period is unaffected by substrate potential disturbances

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